Expand description
SPI0 input delay number control register
Structs§
- SPI0 input delay number control register
Type Aliases§
- Field
DIN0_NUM
reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN0_NUM
writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN1_NUM
reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN1_NUM
writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN2_NUM
reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN2_NUM
writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN3_NUM
reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Field
DIN3_NUM
writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… - Register
DIN_NUM
reader - Register
DIN_NUM
writer