Module esp32c3::spi1::clock

Expand description

SPI1 clock division control register.

Structs

Field CLKCNT_H reader - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).

Field CLKCNT_H writer - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).

Field CLKCNT_L reader - In the master mode it must be equal to spi_mem_clkcnt_N.

Field CLKCNT_L writer - In the master mode it must be equal to spi_mem_clkcnt_N.

Field CLKCNT_N reader - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)

Field CLKCNT_N writer - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)

Field CLK_EQU_SYSCLK reader - reserved

Field CLK_EQU_SYSCLK writer - reserved

SPI1 clock division control register.

Register CLOCK reader

Register CLOCK writer