1#![doc = "Peripheral access API for ESP32-C3 microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
5#![no_std]
6#![cfg_attr(docsrs, feature(doc_cfg))]
7#[doc = r"Number available in the NVIC for configuring priority"]
8pub const NVIC_PRIO_BITS: u8 = 0;
9#[allow(unused_imports)]
10use generic::*;
11#[doc = r"Common register and bit access and modify traits"]
12pub mod generic;
13#[cfg(feature = "rt")]
14extern "C" {
15 fn WIFI_MAC();
16 fn WIFI_MAC_NMI();
17 fn WIFI_PWR();
18 fn WIFI_BB();
19 fn BT_MAC();
20 fn BT_BB();
21 fn BT_BB_NMI();
22 fn RWBT();
23 fn RWBLE();
24 fn RWBT_NMI();
25 fn RWBLE_NMI();
26 fn I2C_MASTER();
27 fn SLC0();
28 fn SLC1();
29 fn APB_CTRL();
30 fn UHCI0();
31 fn GPIO();
32 fn GPIO_NMI();
33 fn SPI1();
34 fn SPI2();
35 fn I2S0();
36 fn UART0();
37 fn UART1();
38 fn LEDC();
39 fn EFUSE();
40 fn TWAI0();
41 fn USB_DEVICE();
42 fn RTC_CORE();
43 fn RMT();
44 fn I2C_EXT0();
45 fn TIMER1();
46 fn TIMER2();
47 fn TG0_T0_LEVEL();
48 fn TG0_WDT_LEVEL();
49 fn TG1_T0_LEVEL();
50 fn TG1_WDT_LEVEL();
51 fn CACHE_IA();
52 fn SYSTIMER_TARGET0();
53 fn SYSTIMER_TARGET1();
54 fn SYSTIMER_TARGET2();
55 fn SPI_MEM_REJECT_CACHE();
56 fn ICACHE_PRELOAD0();
57 fn ICACHE_SYNC0();
58 fn APB_ADC();
59 fn DMA_CH0();
60 fn DMA_CH1();
61 fn DMA_CH2();
62 fn RSA();
63 fn AES();
64 fn SHA();
65 fn FROM_CPU_INTR0();
66 fn FROM_CPU_INTR1();
67 fn FROM_CPU_INTR2();
68 fn FROM_CPU_INTR3();
69 fn ASSIST_DEBUG();
70 fn DMA_APBPERI_PMS();
71 fn CORE0_IRAM0_PMS();
72 fn CORE0_DRAM0_PMS();
73 fn CORE0_PIF_PMS();
74 fn CORE0_PIF_PMS_SIZE();
75 fn BAK_PMS_VIOLATE();
76 fn CACHE_CORE0_ACS();
77}
78#[doc(hidden)]
79#[repr(C)]
80pub union Vector {
81 pub _handler: unsafe extern "C" fn(),
82 pub _reserved: usize,
83}
84#[cfg(feature = "rt")]
85#[doc(hidden)]
86#[link_section = ".rwtext.interrupt"]
87#[no_mangle]
88pub static __EXTERNAL_INTERRUPTS: [Vector; 62] = [
89 Vector { _handler: WIFI_MAC },
90 Vector {
91 _handler: WIFI_MAC_NMI,
92 },
93 Vector { _handler: WIFI_PWR },
94 Vector { _handler: WIFI_BB },
95 Vector { _handler: BT_MAC },
96 Vector { _handler: BT_BB },
97 Vector {
98 _handler: BT_BB_NMI,
99 },
100 Vector { _handler: RWBT },
101 Vector { _handler: RWBLE },
102 Vector { _handler: RWBT_NMI },
103 Vector {
104 _handler: RWBLE_NMI,
105 },
106 Vector {
107 _handler: I2C_MASTER,
108 },
109 Vector { _handler: SLC0 },
110 Vector { _handler: SLC1 },
111 Vector { _handler: APB_CTRL },
112 Vector { _handler: UHCI0 },
113 Vector { _handler: GPIO },
114 Vector { _handler: GPIO_NMI },
115 Vector { _handler: SPI1 },
116 Vector { _handler: SPI2 },
117 Vector { _handler: I2S0 },
118 Vector { _handler: UART0 },
119 Vector { _handler: UART1 },
120 Vector { _handler: LEDC },
121 Vector { _handler: EFUSE },
122 Vector { _handler: TWAI0 },
123 Vector {
124 _handler: USB_DEVICE,
125 },
126 Vector { _handler: RTC_CORE },
127 Vector { _handler: RMT },
128 Vector { _handler: I2C_EXT0 },
129 Vector { _handler: TIMER1 },
130 Vector { _handler: TIMER2 },
131 Vector {
132 _handler: TG0_T0_LEVEL,
133 },
134 Vector {
135 _handler: TG0_WDT_LEVEL,
136 },
137 Vector {
138 _handler: TG1_T0_LEVEL,
139 },
140 Vector {
141 _handler: TG1_WDT_LEVEL,
142 },
143 Vector { _handler: CACHE_IA },
144 Vector {
145 _handler: SYSTIMER_TARGET0,
146 },
147 Vector {
148 _handler: SYSTIMER_TARGET1,
149 },
150 Vector {
151 _handler: SYSTIMER_TARGET2,
152 },
153 Vector {
154 _handler: SPI_MEM_REJECT_CACHE,
155 },
156 Vector {
157 _handler: ICACHE_PRELOAD0,
158 },
159 Vector {
160 _handler: ICACHE_SYNC0,
161 },
162 Vector { _handler: APB_ADC },
163 Vector { _handler: DMA_CH0 },
164 Vector { _handler: DMA_CH1 },
165 Vector { _handler: DMA_CH2 },
166 Vector { _handler: RSA },
167 Vector { _handler: AES },
168 Vector { _handler: SHA },
169 Vector {
170 _handler: FROM_CPU_INTR0,
171 },
172 Vector {
173 _handler: FROM_CPU_INTR1,
174 },
175 Vector {
176 _handler: FROM_CPU_INTR2,
177 },
178 Vector {
179 _handler: FROM_CPU_INTR3,
180 },
181 Vector {
182 _handler: ASSIST_DEBUG,
183 },
184 Vector {
185 _handler: DMA_APBPERI_PMS,
186 },
187 Vector {
188 _handler: CORE0_IRAM0_PMS,
189 },
190 Vector {
191 _handler: CORE0_DRAM0_PMS,
192 },
193 Vector {
194 _handler: CORE0_PIF_PMS,
195 },
196 Vector {
197 _handler: CORE0_PIF_PMS_SIZE,
198 },
199 Vector {
200 _handler: BAK_PMS_VIOLATE,
201 },
202 Vector {
203 _handler: CACHE_CORE0_ACS,
204 },
205];
206#[doc(hidden)]
207pub mod interrupt;
208pub use self::interrupt::Interrupt;
209#[doc = "AES (Advanced Encryption Standard) Accelerator"]
210pub type AES = crate::Periph<aes::RegisterBlock, 0x6003_a000>;
211impl core::fmt::Debug for AES {
212 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
213 f.debug_struct("AES").finish()
214 }
215}
216#[doc = "AES (Advanced Encryption Standard) Accelerator"]
217pub mod aes;
218#[doc = "APB (Advanced Peripheral Bus) Controller"]
219pub type APB_CTRL = crate::Periph<apb_ctrl::RegisterBlock, 0x6002_6000>;
220impl core::fmt::Debug for APB_CTRL {
221 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
222 f.debug_struct("APB_CTRL").finish()
223 }
224}
225#[doc = "APB (Advanced Peripheral Bus) Controller"]
226pub mod apb_ctrl;
227#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
228pub type APB_SARADC = crate::Periph<apb_saradc::RegisterBlock, 0x6004_0000>;
229impl core::fmt::Debug for APB_SARADC {
230 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
231 f.debug_struct("APB_SARADC").finish()
232 }
233}
234#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
235pub mod apb_saradc;
236#[doc = "Debug Assist"]
237pub type ASSIST_DEBUG = crate::Periph<assist_debug::RegisterBlock, 0x600c_e000>;
238impl core::fmt::Debug for ASSIST_DEBUG {
239 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
240 f.debug_struct("ASSIST_DEBUG").finish()
241 }
242}
243#[doc = "Debug Assist"]
244pub mod assist_debug;
245#[doc = "BB Peripheral"]
246pub type BB = crate::Periph<bb::RegisterBlock, 0x6001_d000>;
247impl core::fmt::Debug for BB {
248 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
249 f.debug_struct("BB").finish()
250 }
251}
252#[doc = "BB Peripheral"]
253pub mod bb;
254#[doc = "DMA (Direct Memory Access) Controller"]
255pub type DMA = crate::Periph<dma::RegisterBlock, 0x6003_f000>;
256impl core::fmt::Debug for DMA {
257 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
258 f.debug_struct("DMA").finish()
259 }
260}
261#[doc = "DMA (Direct Memory Access) Controller"]
262pub mod dma;
263#[doc = "Digital Signature"]
264pub type DS = crate::Periph<ds::RegisterBlock, 0x6003_d000>;
265impl core::fmt::Debug for DS {
266 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
267 f.debug_struct("DS").finish()
268 }
269}
270#[doc = "Digital Signature"]
271pub mod ds;
272#[doc = "eFuse Controller"]
273pub type EFUSE = crate::Periph<efuse::RegisterBlock, 0x6000_8800>;
274impl core::fmt::Debug for EFUSE {
275 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
276 f.debug_struct("EFUSE").finish()
277 }
278}
279#[doc = "eFuse Controller"]
280pub mod efuse;
281#[doc = "External Memory"]
282pub type EXTMEM = crate::Periph<extmem::RegisterBlock, 0x600c_4000>;
283impl core::fmt::Debug for EXTMEM {
284 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
285 f.debug_struct("EXTMEM").finish()
286 }
287}
288#[doc = "External Memory"]
289pub mod extmem;
290#[doc = "External memory cache MMU table"]
291pub type MMU_TABLE = crate::Periph<mmu_table::RegisterBlock, 0x600c_5000>;
292impl core::fmt::Debug for MMU_TABLE {
293 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
294 f.debug_struct("MMU_TABLE").finish()
295 }
296}
297#[doc = "External memory cache MMU table"]
298pub mod mmu_table;
299#[doc = "General Purpose Input/Output"]
300pub type GPIO = crate::Periph<gpio::RegisterBlock, 0x6000_4000>;
301impl core::fmt::Debug for GPIO {
302 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
303 f.debug_struct("GPIO").finish()
304 }
305}
306#[doc = "General Purpose Input/Output"]
307pub mod gpio;
308#[doc = "Sigma-Delta Modulation"]
309pub type GPIO_SD = crate::Periph<gpio_sd::RegisterBlock, 0x6000_4f00>;
310impl core::fmt::Debug for GPIO_SD {
311 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
312 f.debug_struct("GPIO_SD").finish()
313 }
314}
315#[doc = "Sigma-Delta Modulation"]
316pub mod gpio_sd;
317#[doc = "need des"]
318pub type FE2 = crate::Periph<fe2::RegisterBlock, 0x6000_5000>;
319impl core::fmt::Debug for FE2 {
320 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
321 f.debug_struct("FE2").finish()
322 }
323}
324#[doc = "need des"]
325pub mod fe2;
326#[doc = "need des"]
327pub type FE = crate::Periph<fe::RegisterBlock, 0x6000_6000>;
328impl core::fmt::Debug for FE {
329 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
330 f.debug_struct("FE").finish()
331 }
332}
333#[doc = "need des"]
334pub mod fe;
335#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
336pub type HMAC = crate::Periph<hmac::RegisterBlock, 0x6003_e000>;
337impl core::fmt::Debug for HMAC {
338 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
339 f.debug_struct("HMAC").finish()
340 }
341}
342#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
343pub mod hmac;
344#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
345pub type I2C0 = crate::Periph<i2c0::RegisterBlock, 0x6001_3000>;
346impl core::fmt::Debug for I2C0 {
347 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
348 f.debug_struct("I2C0").finish()
349 }
350}
351#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
352pub mod i2c0;
353#[doc = "I2S (Inter-IC Sound) Controller 0"]
354pub type I2S0 = crate::Periph<i2s0::RegisterBlock, 0x6002_d000>;
355impl core::fmt::Debug for I2S0 {
356 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
357 f.debug_struct("I2S0").finish()
358 }
359}
360#[doc = "I2S (Inter-IC Sound) Controller 0"]
361pub mod i2s0;
362#[doc = "Interrupt Controller (Core 0)"]
363pub type INTERRUPT_CORE0 = crate::Periph<interrupt_core0::RegisterBlock, 0x600c_2000>;
364impl core::fmt::Debug for INTERRUPT_CORE0 {
365 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
366 f.debug_struct("INTERRUPT_CORE0").finish()
367 }
368}
369#[doc = "Interrupt Controller (Core 0)"]
370pub mod interrupt_core0;
371#[doc = "Input/Output Multiplexer"]
372pub type IO_MUX = crate::Periph<io_mux::RegisterBlock, 0x6000_9000>;
373impl core::fmt::Debug for IO_MUX {
374 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
375 f.debug_struct("IO_MUX").finish()
376 }
377}
378#[doc = "Input/Output Multiplexer"]
379pub mod io_mux;
380#[doc = "I2C_MST_ANA Peripheral"]
381pub type I2C_ANA_MST = crate::Periph<i2c_ana_mst::RegisterBlock, 0x6000_e040>;
382impl core::fmt::Debug for I2C_ANA_MST {
383 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
384 f.debug_struct("I2C_ANA_MST").finish()
385 }
386}
387#[doc = "I2C_MST_ANA Peripheral"]
388pub mod i2c_ana_mst;
389#[doc = "LED Control PWM (Pulse Width Modulation)"]
390pub type LEDC = crate::Periph<ledc::RegisterBlock, 0x6001_9000>;
391impl core::fmt::Debug for LEDC {
392 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
393 f.debug_struct("LEDC").finish()
394 }
395}
396#[doc = "LED Control PWM (Pulse Width Modulation)"]
397pub mod ledc;
398#[doc = "NRX Peripheral"]
399pub type NRX = crate::Periph<nrx::RegisterBlock, 0x6001_cc00>;
400impl core::fmt::Debug for NRX {
401 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
402 f.debug_struct("NRX").finish()
403 }
404}
405#[doc = "NRX Peripheral"]
406pub mod nrx;
407#[doc = "Remote Control"]
408pub type RMT = crate::Periph<rmt::RegisterBlock, 0x6001_6000>;
409impl core::fmt::Debug for RMT {
410 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
411 f.debug_struct("RMT").finish()
412 }
413}
414#[doc = "Remote Control"]
415pub mod rmt;
416#[doc = "Hardware Random Number Generator"]
417pub type RNG = crate::Periph<rng::RegisterBlock, 0x6002_6000>;
418impl core::fmt::Debug for RNG {
419 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
420 f.debug_struct("RNG").finish()
421 }
422}
423#[doc = "Hardware Random Number Generator"]
424pub mod rng;
425#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
426pub type RSA = crate::Periph<rsa::RegisterBlock, 0x6003_c000>;
427impl core::fmt::Debug for RSA {
428 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
429 f.debug_struct("RSA").finish()
430 }
431}
432#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
433pub mod rsa;
434#[doc = "Real-Time Clock Control"]
435pub type RTC_CNTL = crate::Periph<rtc_cntl::RegisterBlock, 0x6000_8000>;
436impl core::fmt::Debug for RTC_CNTL {
437 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
438 f.debug_struct("RTC_CNTL").finish()
439 }
440}
441#[doc = "Real-Time Clock Control"]
442pub mod rtc_cntl;
443#[doc = "SENSITIVE Peripheral"]
444pub type SENSITIVE = crate::Periph<sensitive::RegisterBlock, 0x600c_1000>;
445impl core::fmt::Debug for SENSITIVE {
446 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
447 f.debug_struct("SENSITIVE").finish()
448 }
449}
450#[doc = "SENSITIVE Peripheral"]
451pub mod sensitive;
452#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
453pub type SHA = crate::Periph<sha::RegisterBlock, 0x6003_b000>;
454impl core::fmt::Debug for SHA {
455 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
456 f.debug_struct("SHA").finish()
457 }
458}
459#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
460pub mod sha;
461#[doc = "SPI (Serial Peripheral Interface) Controller 0"]
462pub type SPI0 = crate::Periph<spi0::RegisterBlock, 0x6000_3000>;
463impl core::fmt::Debug for SPI0 {
464 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
465 f.debug_struct("SPI0").finish()
466 }
467}
468#[doc = "SPI (Serial Peripheral Interface) Controller 0"]
469pub mod spi0;
470#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
471pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x6000_2000>;
472impl core::fmt::Debug for SPI1 {
473 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
474 f.debug_struct("SPI1").finish()
475 }
476}
477#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
478pub mod spi1;
479#[doc = "SPI (Serial Peripheral Interface) Controller 2"]
480pub type SPI2 = crate::Periph<spi2::RegisterBlock, 0x6002_4000>;
481impl core::fmt::Debug for SPI2 {
482 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
483 f.debug_struct("SPI2").finish()
484 }
485}
486#[doc = "SPI (Serial Peripheral Interface) Controller 2"]
487pub mod spi2;
488#[doc = "System Configuration Registers"]
489pub type SYSTEM = crate::Periph<system::RegisterBlock, 0x600c_0000>;
490impl core::fmt::Debug for SYSTEM {
491 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
492 f.debug_struct("SYSTEM").finish()
493 }
494}
495#[doc = "System Configuration Registers"]
496pub mod system;
497#[doc = "System Timer"]
498pub type SYSTIMER = crate::Periph<systimer::RegisterBlock, 0x6002_3000>;
499impl core::fmt::Debug for SYSTIMER {
500 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
501 f.debug_struct("SYSTIMER").finish()
502 }
503}
504#[doc = "System Timer"]
505pub mod systimer;
506#[doc = "Timer Group 0"]
507pub type TIMG0 = crate::Periph<timg0::RegisterBlock, 0x6001_f000>;
508impl core::fmt::Debug for TIMG0 {
509 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
510 f.debug_struct("TIMG0").finish()
511 }
512}
513#[doc = "Timer Group 0"]
514pub mod timg0;
515#[doc = "Timer Group 1"]
516pub type TIMG1 = crate::Periph<timg0::RegisterBlock, 0x6002_0000>;
517impl core::fmt::Debug for TIMG1 {
518 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
519 f.debug_struct("TIMG1").finish()
520 }
521}
522#[doc = "Timer Group 1"]
523pub use self::timg0 as timg1;
524#[doc = "Two-Wire Automotive Interface"]
525pub type TWAI0 = crate::Periph<twai0::RegisterBlock, 0x6002_b000>;
526impl core::fmt::Debug for TWAI0 {
527 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
528 f.debug_struct("TWAI0").finish()
529 }
530}
531#[doc = "Two-Wire Automotive Interface"]
532pub mod twai0;
533#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
534pub type UART0 = crate::Periph<uart0::RegisterBlock, 0x6000_0000>;
535impl core::fmt::Debug for UART0 {
536 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
537 f.debug_struct("UART0").finish()
538 }
539}
540#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
541pub mod uart0;
542#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
543pub type UART1 = crate::Periph<uart0::RegisterBlock, 0x6001_0000>;
544impl core::fmt::Debug for UART1 {
545 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
546 f.debug_struct("UART1").finish()
547 }
548}
549#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
550pub use self::uart0 as uart1;
551#[doc = "Universal Host Controller Interface 0"]
552pub type UHCI0 = crate::Periph<uhci0::RegisterBlock, 0x6001_4000>;
553impl core::fmt::Debug for UHCI0 {
554 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
555 f.debug_struct("UHCI0").finish()
556 }
557}
558#[doc = "Universal Host Controller Interface 0"]
559pub mod uhci0;
560#[doc = "Full-speed USB Serial/JTAG Controller"]
561pub type USB_DEVICE = crate::Periph<usb_device::RegisterBlock, 0x6004_3000>;
562impl core::fmt::Debug for USB_DEVICE {
563 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
564 f.debug_struct("USB_DEVICE").finish()
565 }
566}
567#[doc = "Full-speed USB Serial/JTAG Controller"]
568pub mod usb_device;
569#[doc = "XTS-AES-128 Flash Encryption"]
570pub type XTS_AES = crate::Periph<xts_aes::RegisterBlock, 0x600c_c000>;
571impl core::fmt::Debug for XTS_AES {
572 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
573 f.debug_struct("XTS_AES").finish()
574 }
575}
576#[doc = "XTS-AES-128 Flash Encryption"]
577pub mod xts_aes;