esp32c3/twai0/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `RX_INT_ST` reader - Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO."]
4pub type RX_INT_ST_R = crate::BitReader;
5#[doc = "Field `TX_INT_ST` reader - Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute."]
6pub type TX_INT_ST_R = crate::BitReader;
7#[doc = "Field `ERR_WARN_INT_ST` reader - Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0)."]
8pub type ERR_WARN_INT_ST_R = crate::BitReader;
9#[doc = "Field `OVERRUN_INT_ST` reader - Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO."]
10pub type OVERRUN_INT_ST_R = crate::BitReader;
11#[doc = "Field `ERR_PASSIVE_INT_ST` reader - Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters."]
12pub type ERR_PASSIVE_INT_ST_R = crate::BitReader;
13#[doc = "Field `ARB_LOST_INT_ST` reader - Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated."]
14pub type ARB_LOST_INT_ST_R = crate::BitReader;
15#[doc = "Field `BUS_ERR_INT_ST` reader - Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus."]
16pub type BUS_ERR_INT_ST_R = crate::BitReader;
17impl R {
18    #[doc = "Bit 0 - Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO."]
19    #[inline(always)]
20    pub fn rx_int_st(&self) -> RX_INT_ST_R {
21        RX_INT_ST_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute."]
24    #[inline(always)]
25    pub fn tx_int_st(&self) -> TX_INT_ST_R {
26        TX_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0)."]
29    #[inline(always)]
30    pub fn err_warn_int_st(&self) -> ERR_WARN_INT_ST_R {
31        ERR_WARN_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
32    }
33    #[doc = "Bit 3 - Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO."]
34    #[inline(always)]
35    pub fn overrun_int_st(&self) -> OVERRUN_INT_ST_R {
36        OVERRUN_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
37    }
38    #[doc = "Bit 5 - Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters."]
39    #[inline(always)]
40    pub fn err_passive_int_st(&self) -> ERR_PASSIVE_INT_ST_R {
41        ERR_PASSIVE_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
42    }
43    #[doc = "Bit 6 - Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated."]
44    #[inline(always)]
45    pub fn arb_lost_int_st(&self) -> ARB_LOST_INT_ST_R {
46        ARB_LOST_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
47    }
48    #[doc = "Bit 7 - Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus."]
49    #[inline(always)]
50    pub fn bus_err_int_st(&self) -> BUS_ERR_INT_ST_R {
51        BUS_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("INT_RAW")
58            .field("rx_int_st", &self.rx_int_st())
59            .field("tx_int_st", &self.tx_int_st())
60            .field("err_warn_int_st", &self.err_warn_int_st())
61            .field("overrun_int_st", &self.overrun_int_st())
62            .field("err_passive_int_st", &self.err_passive_int_st())
63            .field("arb_lost_int_st", &self.arb_lost_int_st())
64            .field("bus_err_int_st", &self.bus_err_int_st())
65            .finish()
66    }
67}
68#[doc = "Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
69pub struct INT_RAW_SPEC;
70impl crate::RegisterSpec for INT_RAW_SPEC {
71    type Ux = u32;
72}
73#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
74impl crate::Readable for INT_RAW_SPEC {}
75#[doc = "`reset()` method sets INT_RAW to value 0"]
76impl crate::Resettable for INT_RAW_SPEC {
77    const RESET_VALUE: u32 = 0;
78}
esp32c3/twai0/int_raw.rs

esp32c3/twai0/
int_raw.rs
