esp32c3/timg0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `T(0-0)` writer - t%s_int_clr"]
4pub type T_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `WDT` writer - wdt_int_clr"]
6pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[cfg(feature = "impl-register-debug")]
8impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        write!(f, "(not readable)")
11    }
12}
13impl W {
14    #[doc = "t(0-0)_int_clr"]
15    #[doc = ""]
16    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
17    #[inline(always)]
18    pub fn t(&mut self, n: u8) -> T_W<INT_CLR_SPEC> {
19        #[allow(clippy::no_effect)]
20        [(); 1][n as usize];
21        T_W::new(self, n * 0)
22    }
23    #[doc = "Bit 0 - t0_int_clr"]
24    #[inline(always)]
25    pub fn t0(&mut self) -> T_W<INT_CLR_SPEC> {
26        T_W::new(self, 0)
27    }
28    #[doc = "Bit 1 - wdt_int_clr"]
29    #[inline(always)]
30    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
31        WDT_W::new(self, 1)
32    }
33}
34#[doc = "INT_CLR_TIMG_REG\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct INT_CLR_SPEC;
36impl crate::RegisterSpec for INT_CLR_SPEC {
37    type Ux = u32;
38}
39#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
40impl crate::Writable for INT_CLR_SPEC {
41    type Safety = crate::Unsafe;
42    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03;
44}
45#[doc = "`reset()` method sets INT_CLR to value 0"]
46impl crate::Resettable for INT_CLR_SPEC {
47    const RESET_VALUE: u32 = 0;
48}
esp32c3/timg0/int_clr.rs

esp32c3/timg0/
int_clr.rs
