1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
6pub type DOUTDIN_R = crate::BitReader;
7#[doc = "Field `DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
8pub type DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `QPI_MODE` reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
10pub type QPI_MODE_R = crate::BitReader;
11#[doc = "Field `QPI_MODE` writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
12pub type QPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
14pub type TSCK_I_EDGE_R = crate::BitReader;
15#[doc = "Field `TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
16pub type TSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
18pub type CS_HOLD_R = crate::BitReader;
19#[doc = "Field `CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
20pub type CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
22pub type CS_SETUP_R = crate::BitReader;
23#[doc = "Field `CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
24pub type CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
26pub type RSCK_I_EDGE_R = crate::BitReader;
27#[doc = "Field `RSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
28pub type RSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
30pub type CK_OUT_EDGE_R = crate::BitReader;
31#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
32pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
34pub type FWRITE_DUAL_R = crate::BitReader;
35#[doc = "Field `FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
36pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
38pub type FWRITE_QUAD_R = crate::BitReader;
39#[doc = "Field `FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
40pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `USR_CONF_NXT` reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
42pub type USR_CONF_NXT_R = crate::BitReader;
43#[doc = "Field `USR_CONF_NXT` writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
44pub type USR_CONF_NXT_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
46pub type SIO_R = crate::BitReader;
47#[doc = "Field `SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
48pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
50pub type USR_MISO_HIGHPART_R = crate::BitReader;
51#[doc = "Field `USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
52pub type USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
54pub type USR_MOSI_HIGHPART_R = crate::BitReader;
55#[doc = "Field `USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
56pub type USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
58pub type USR_DUMMY_IDLE_R = crate::BitReader;
59#[doc = "Field `USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
60pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `USR_MOSI` reader - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
62pub type USR_MOSI_R = crate::BitReader;
63#[doc = "Field `USR_MOSI` writer - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
64pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `USR_MISO` reader - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
66pub type USR_MISO_R = crate::BitReader;
67#[doc = "Field `USR_MISO` writer - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
68pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
70pub type USR_DUMMY_R = crate::BitReader;
71#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
72pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `USR_ADDR` reader - This bit enable the address phase of an operation. Can be configured in CONF state."]
74pub type USR_ADDR_R = crate::BitReader;
75#[doc = "Field `USR_ADDR` writer - This bit enable the address phase of an operation. Can be configured in CONF state."]
76pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `USR_COMMAND` reader - This bit enable the command phase of an operation. Can be configured in CONF state."]
78pub type USR_COMMAND_R = crate::BitReader;
79#[doc = "Field `USR_COMMAND` writer - This bit enable the command phase of an operation. Can be configured in CONF state."]
80pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
81impl R {
82 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
83 #[inline(always)]
84 pub fn doutdin(&self) -> DOUTDIN_R {
85 DOUTDIN_R::new((self.bits & 1) != 0)
86 }
87 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
88 #[inline(always)]
89 pub fn qpi_mode(&self) -> QPI_MODE_R {
90 QPI_MODE_R::new(((self.bits >> 3) & 1) != 0)
91 }
92 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
93 #[inline(always)]
94 pub fn tsck_i_edge(&self) -> TSCK_I_EDGE_R {
95 TSCK_I_EDGE_R::new(((self.bits >> 5) & 1) != 0)
96 }
97 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
98 #[inline(always)]
99 pub fn cs_hold(&self) -> CS_HOLD_R {
100 CS_HOLD_R::new(((self.bits >> 6) & 1) != 0)
101 }
102 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
103 #[inline(always)]
104 pub fn cs_setup(&self) -> CS_SETUP_R {
105 CS_SETUP_R::new(((self.bits >> 7) & 1) != 0)
106 }
107 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
108 #[inline(always)]
109 pub fn rsck_i_edge(&self) -> RSCK_I_EDGE_R {
110 RSCK_I_EDGE_R::new(((self.bits >> 8) & 1) != 0)
111 }
112 #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
113 #[inline(always)]
114 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
115 CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
116 }
117 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
118 #[inline(always)]
119 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
120 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
121 }
122 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
123 #[inline(always)]
124 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
125 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
126 }
127 #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
128 #[inline(always)]
129 pub fn usr_conf_nxt(&self) -> USR_CONF_NXT_R {
130 USR_CONF_NXT_R::new(((self.bits >> 15) & 1) != 0)
131 }
132 #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
133 #[inline(always)]
134 pub fn sio(&self) -> SIO_R {
135 SIO_R::new(((self.bits >> 17) & 1) != 0)
136 }
137 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
138 #[inline(always)]
139 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
140 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
141 }
142 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
143 #[inline(always)]
144 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
145 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
146 }
147 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
148 #[inline(always)]
149 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
150 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
151 }
152 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
153 #[inline(always)]
154 pub fn usr_mosi(&self) -> USR_MOSI_R {
155 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
156 }
157 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
158 #[inline(always)]
159 pub fn usr_miso(&self) -> USR_MISO_R {
160 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
161 }
162 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
163 #[inline(always)]
164 pub fn usr_dummy(&self) -> USR_DUMMY_R {
165 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
166 }
167 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
168 #[inline(always)]
169 pub fn usr_addr(&self) -> USR_ADDR_R {
170 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
171 }
172 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
173 #[inline(always)]
174 pub fn usr_command(&self) -> USR_COMMAND_R {
175 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
176 }
177}
178#[cfg(feature = "impl-register-debug")]
179impl core::fmt::Debug for R {
180 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
181 f.debug_struct("USER")
182 .field("doutdin", &self.doutdin())
183 .field("qpi_mode", &self.qpi_mode())
184 .field("tsck_i_edge", &self.tsck_i_edge())
185 .field("cs_hold", &self.cs_hold())
186 .field("cs_setup", &self.cs_setup())
187 .field("rsck_i_edge", &self.rsck_i_edge())
188 .field("ck_out_edge", &self.ck_out_edge())
189 .field("fwrite_dual", &self.fwrite_dual())
190 .field("fwrite_quad", &self.fwrite_quad())
191 .field("usr_conf_nxt", &self.usr_conf_nxt())
192 .field("sio", &self.sio())
193 .field("usr_miso_highpart", &self.usr_miso_highpart())
194 .field("usr_mosi_highpart", &self.usr_mosi_highpart())
195 .field("usr_dummy_idle", &self.usr_dummy_idle())
196 .field("usr_mosi", &self.usr_mosi())
197 .field("usr_miso", &self.usr_miso())
198 .field("usr_dummy", &self.usr_dummy())
199 .field("usr_addr", &self.usr_addr())
200 .field("usr_command", &self.usr_command())
201 .finish()
202 }
203}
204impl W {
205 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
206 #[inline(always)]
207 pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
208 DOUTDIN_W::new(self, 0)
209 }
210 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
211 #[inline(always)]
212 pub fn qpi_mode(&mut self) -> QPI_MODE_W<USER_SPEC> {
213 QPI_MODE_W::new(self, 3)
214 }
215 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
216 #[inline(always)]
217 pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<USER_SPEC> {
218 TSCK_I_EDGE_W::new(self, 5)
219 }
220 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
221 #[inline(always)]
222 pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
223 CS_HOLD_W::new(self, 6)
224 }
225 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
226 #[inline(always)]
227 pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
228 CS_SETUP_W::new(self, 7)
229 }
230 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
231 #[inline(always)]
232 pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<USER_SPEC> {
233 RSCK_I_EDGE_W::new(self, 8)
234 }
235 #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
236 #[inline(always)]
237 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
238 CK_OUT_EDGE_W::new(self, 9)
239 }
240 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
241 #[inline(always)]
242 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
243 FWRITE_DUAL_W::new(self, 12)
244 }
245 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
246 #[inline(always)]
247 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
248 FWRITE_QUAD_W::new(self, 13)
249 }
250 #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
251 #[inline(always)]
252 pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<USER_SPEC> {
253 USR_CONF_NXT_W::new(self, 15)
254 }
255 #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
256 #[inline(always)]
257 pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
258 SIO_W::new(self, 17)
259 }
260 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
261 #[inline(always)]
262 pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
263 USR_MISO_HIGHPART_W::new(self, 24)
264 }
265 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
266 #[inline(always)]
267 pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
268 USR_MOSI_HIGHPART_W::new(self, 25)
269 }
270 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
271 #[inline(always)]
272 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
273 USR_DUMMY_IDLE_W::new(self, 26)
274 }
275 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
276 #[inline(always)]
277 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
278 USR_MOSI_W::new(self, 27)
279 }
280 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
281 #[inline(always)]
282 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
283 USR_MISO_W::new(self, 28)
284 }
285 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
286 #[inline(always)]
287 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
288 USR_DUMMY_W::new(self, 29)
289 }
290 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
291 #[inline(always)]
292 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
293 USR_ADDR_W::new(self, 30)
294 }
295 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
296 #[inline(always)]
297 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
298 USR_COMMAND_W::new(self, 31)
299 }
300}
301#[doc = "SPI USER control register\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
302pub struct USER_SPEC;
303impl crate::RegisterSpec for USER_SPEC {
304 type Ux = u32;
305}
306#[doc = "`read()` method returns [`user::R`](R) reader structure"]
307impl crate::Readable for USER_SPEC {}
308#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
309impl crate::Writable for USER_SPEC {
310 type Safety = crate::Unsafe;
311 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
312 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
313}
314#[doc = "`reset()` method sets USER to value 0x8000_00c0"]
315impl crate::Resettable for USER_SPEC {
316 const RESET_VALUE: u32 = 0x8000_00c0;
317}