1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `CS0_DIS` reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
6pub type CS0_DIS_R = crate::BitReader;
7#[doc = "Field `CS0_DIS` writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
8pub type CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CS1_DIS` reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
10pub type CS1_DIS_R = crate::BitReader;
11#[doc = "Field `CS1_DIS` writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
12pub type CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS2_DIS` reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
14pub type CS2_DIS_R = crate::BitReader;
15#[doc = "Field `CS2_DIS` writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
16pub type CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CS3_DIS` reader - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
18pub type CS3_DIS_R = crate::BitReader;
19#[doc = "Field `CS3_DIS` writer - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
20pub type CS3_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS4_DIS` reader - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
22pub type CS4_DIS_R = crate::BitReader;
23#[doc = "Field `CS4_DIS` writer - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
24pub type CS4_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS5_DIS` reader - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
26pub type CS5_DIS_R = crate::BitReader;
27#[doc = "Field `CS5_DIS` writer - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
28pub type CS5_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CK_DIS` reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
30pub type CK_DIS_R = crate::BitReader;
31#[doc = "Field `CK_DIS` writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
32pub type CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
34pub type MASTER_CS_POL_R = crate::FieldReader;
35#[doc = "Field `MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
36pub type MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
37#[doc = "Field `SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
38pub type SLAVE_CS_POL_R = crate::BitReader;
39#[doc = "Field `SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
40pub type SLAVE_CS_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
42pub type CK_IDLE_EDGE_R = crate::BitReader;
43#[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
44pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set. Can be configured in CONF state."]
46pub type CS_KEEP_ACTIVE_R = crate::BitReader;
47#[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set. Can be configured in CONF state."]
48pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `QUAD_DIN_PIN_SWAP` reader - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
50pub type QUAD_DIN_PIN_SWAP_R = crate::BitReader;
51#[doc = "Field `QUAD_DIN_PIN_SWAP` writer - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
52pub type QUAD_DIN_PIN_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
55 #[inline(always)]
56 pub fn cs0_dis(&self) -> CS0_DIS_R {
57 CS0_DIS_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
60 #[inline(always)]
61 pub fn cs1_dis(&self) -> CS1_DIS_R {
62 CS1_DIS_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
65 #[inline(always)]
66 pub fn cs2_dis(&self) -> CS2_DIS_R {
67 CS2_DIS_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
70 #[inline(always)]
71 pub fn cs3_dis(&self) -> CS3_DIS_R {
72 CS3_DIS_R::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
75 #[inline(always)]
76 pub fn cs4_dis(&self) -> CS4_DIS_R {
77 CS4_DIS_R::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
80 #[inline(always)]
81 pub fn cs5_dis(&self) -> CS5_DIS_R {
82 CS5_DIS_R::new(((self.bits >> 5) & 1) != 0)
83 }
84 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
85 #[inline(always)]
86 pub fn ck_dis(&self) -> CK_DIS_R {
87 CK_DIS_R::new(((self.bits >> 6) & 1) != 0)
88 }
89 #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
90 #[inline(always)]
91 pub fn master_cs_pol(&self) -> MASTER_CS_POL_R {
92 MASTER_CS_POL_R::new(((self.bits >> 7) & 0x3f) as u8)
93 }
94 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
95 #[inline(always)]
96 pub fn slave_cs_pol(&self) -> SLAVE_CS_POL_R {
97 SLAVE_CS_POL_R::new(((self.bits >> 23) & 1) != 0)
98 }
99 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
100 #[inline(always)]
101 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
102 CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0)
103 }
104 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
105 #[inline(always)]
106 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
107 CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
108 }
109 #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
110 #[inline(always)]
111 pub fn quad_din_pin_swap(&self) -> QUAD_DIN_PIN_SWAP_R {
112 QUAD_DIN_PIN_SWAP_R::new(((self.bits >> 31) & 1) != 0)
113 }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("MISC")
119 .field("cs0_dis", &self.cs0_dis())
120 .field("cs1_dis", &self.cs1_dis())
121 .field("cs2_dis", &self.cs2_dis())
122 .field("cs3_dis", &self.cs3_dis())
123 .field("cs4_dis", &self.cs4_dis())
124 .field("cs5_dis", &self.cs5_dis())
125 .field("ck_dis", &self.ck_dis())
126 .field("master_cs_pol", &self.master_cs_pol())
127 .field("slave_cs_pol", &self.slave_cs_pol())
128 .field("ck_idle_edge", &self.ck_idle_edge())
129 .field("cs_keep_active", &self.cs_keep_active())
130 .field("quad_din_pin_swap", &self.quad_din_pin_swap())
131 .finish()
132 }
133}
134impl W {
135 #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
136 #[inline(always)]
137 pub fn cs0_dis(&mut self) -> CS0_DIS_W<MISC_SPEC> {
138 CS0_DIS_W::new(self, 0)
139 }
140 #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
141 #[inline(always)]
142 pub fn cs1_dis(&mut self) -> CS1_DIS_W<MISC_SPEC> {
143 CS1_DIS_W::new(self, 1)
144 }
145 #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
146 #[inline(always)]
147 pub fn cs2_dis(&mut self) -> CS2_DIS_W<MISC_SPEC> {
148 CS2_DIS_W::new(self, 2)
149 }
150 #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
151 #[inline(always)]
152 pub fn cs3_dis(&mut self) -> CS3_DIS_W<MISC_SPEC> {
153 CS3_DIS_W::new(self, 3)
154 }
155 #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
156 #[inline(always)]
157 pub fn cs4_dis(&mut self) -> CS4_DIS_W<MISC_SPEC> {
158 CS4_DIS_W::new(self, 4)
159 }
160 #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
161 #[inline(always)]
162 pub fn cs5_dis(&mut self) -> CS5_DIS_W<MISC_SPEC> {
163 CS5_DIS_W::new(self, 5)
164 }
165 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
166 #[inline(always)]
167 pub fn ck_dis(&mut self) -> CK_DIS_W<MISC_SPEC> {
168 CK_DIS_W::new(self, 6)
169 }
170 #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
171 #[inline(always)]
172 pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<MISC_SPEC> {
173 MASTER_CS_POL_W::new(self, 7)
174 }
175 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
176 #[inline(always)]
177 pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<MISC_SPEC> {
178 SLAVE_CS_POL_W::new(self, 23)
179 }
180 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
181 #[inline(always)]
182 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
183 CK_IDLE_EDGE_W::new(self, 29)
184 }
185 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
186 #[inline(always)]
187 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
188 CS_KEEP_ACTIVE_W::new(self, 30)
189 }
190 #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
191 #[inline(always)]
192 pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<MISC_SPEC> {
193 QUAD_DIN_PIN_SWAP_W::new(self, 31)
194 }
195}
196#[doc = "SPI misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
197pub struct MISC_SPEC;
198impl crate::RegisterSpec for MISC_SPEC {
199 type Ux = u32;
200}
201#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
202impl crate::Readable for MISC_SPEC {}
203#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
204impl crate::Writable for MISC_SPEC {
205 type Safety = crate::Unsafe;
206 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
207 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
208}
209#[doc = "`reset()` method sets MISC to value 0x3e"]
210impl crate::Resettable for MISC_SPEC {
211 const RESET_VALUE: u32 = 0x3e;
212}