1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `FDUMMY_OUT` reader - In the dummy phase the signal level of spi is output by the spi controller."]
6pub type FDUMMY_OUT_R = crate::BitReader;
7#[doc = "Field `FDUMMY_OUT` writer - In the dummy phase the signal level of spi is output by the spi controller."]
8pub type FDUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable"]
10pub type FCMD_DUAL_R = crate::BitReader;
11#[doc = "Field `FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable"]
12pub type FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"]
14pub type FCMD_QUAD_R = crate::BitReader;
15#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"]
16pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FASTRD_MODE` reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
18pub type FASTRD_MODE_R = crate::BitReader;
19#[doc = "Field `FASTRD_MODE` writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
20pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
22pub type FREAD_DUAL_R = crate::BitReader;
23#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
24pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"]
26pub type Q_POL_R = crate::BitReader;
27#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"]
28pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"]
30pub type D_POL_R = crate::BitReader;
31#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"]
32pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
34pub type FREAD_QUAD_R = crate::BitReader;
35#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
36pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
38pub type WP_R = crate::BitReader;
39#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
40pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
42pub type FREAD_DIO_R = crate::BitReader;
43#[doc = "Field `FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
44pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
46pub type FREAD_QIO_R = crate::BitReader;
47#[doc = "Field `FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
48pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
51 #[inline(always)]
52 pub fn fdummy_out(&self) -> FDUMMY_OUT_R {
53 FDUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0)
54 }
55 #[doc = "Bit 7 - Apply 2 signals during command phase 1:enable 0: disable"]
56 #[inline(always)]
57 pub fn fcmd_dual(&self) -> FCMD_DUAL_R {
58 FCMD_DUAL_R::new(((self.bits >> 7) & 1) != 0)
59 }
60 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
61 #[inline(always)]
62 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
63 FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0)
64 }
65 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
66 #[inline(always)]
67 pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
68 FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
69 }
70 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
71 #[inline(always)]
72 pub fn fread_dual(&self) -> FREAD_DUAL_R {
73 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
74 }
75 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
76 #[inline(always)]
77 pub fn q_pol(&self) -> Q_POL_R {
78 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
79 }
80 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
81 #[inline(always)]
82 pub fn d_pol(&self) -> D_POL_R {
83 D_POL_R::new(((self.bits >> 19) & 1) != 0)
84 }
85 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
86 #[inline(always)]
87 pub fn fread_quad(&self) -> FREAD_QUAD_R {
88 FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
89 }
90 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
91 #[inline(always)]
92 pub fn wp(&self) -> WP_R {
93 WP_R::new(((self.bits >> 21) & 1) != 0)
94 }
95 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
96 #[inline(always)]
97 pub fn fread_dio(&self) -> FREAD_DIO_R {
98 FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
99 }
100 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
101 #[inline(always)]
102 pub fn fread_qio(&self) -> FREAD_QIO_R {
103 FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("CTRL")
110 .field("fdummy_out", &self.fdummy_out())
111 .field("fcmd_dual", &self.fcmd_dual())
112 .field("fcmd_quad", &self.fcmd_quad())
113 .field("fastrd_mode", &self.fastrd_mode())
114 .field("fread_dual", &self.fread_dual())
115 .field("q_pol", &self.q_pol())
116 .field("d_pol", &self.d_pol())
117 .field("fread_quad", &self.fread_quad())
118 .field("wp", &self.wp())
119 .field("fread_dio", &self.fread_dio())
120 .field("fread_qio", &self.fread_qio())
121 .finish()
122 }
123}
124impl W {
125 #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
126 #[inline(always)]
127 pub fn fdummy_out(&mut self) -> FDUMMY_OUT_W<CTRL_SPEC> {
128 FDUMMY_OUT_W::new(self, 3)
129 }
130 #[doc = "Bit 7 - Apply 2 signals during command phase 1:enable 0: disable"]
131 #[inline(always)]
132 pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
133 FCMD_DUAL_W::new(self, 7)
134 }
135 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
136 #[inline(always)]
137 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
138 FCMD_QUAD_W::new(self, 8)
139 }
140 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
141 #[inline(always)]
142 pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
143 FASTRD_MODE_W::new(self, 13)
144 }
145 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
146 #[inline(always)]
147 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
148 FREAD_DUAL_W::new(self, 14)
149 }
150 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
151 #[inline(always)]
152 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
153 Q_POL_W::new(self, 18)
154 }
155 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
156 #[inline(always)]
157 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
158 D_POL_W::new(self, 19)
159 }
160 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
161 #[inline(always)]
162 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
163 FREAD_QUAD_W::new(self, 20)
164 }
165 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
166 #[inline(always)]
167 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
168 WP_W::new(self, 21)
169 }
170 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
171 #[inline(always)]
172 pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
173 FREAD_DIO_W::new(self, 23)
174 }
175 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
176 #[inline(always)]
177 pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
178 FREAD_QIO_W::new(self, 24)
179 }
180}
181#[doc = "SPI0 control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct CTRL_SPEC;
183impl crate::RegisterSpec for CTRL_SPEC {
184 type Ux = u32;
185}
186#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
187impl crate::Readable for CTRL_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
189impl crate::Writable for CTRL_SPEC {
190 type Safety = crate::Unsafe;
191 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
193}
194#[doc = "`reset()` method sets CTRL to value 0x002c_2000"]
195impl crate::Resettable for CTRL_SPEC {
196 const RESET_VALUE: u32 = 0x002c_2000;
197}