esp32c3/rtc_cntl/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `SLP_WAKEUP` reader - sleep wakeup interrupt raw"]
4pub type SLP_WAKEUP_R = crate::BitReader;
5#[doc = "Field `SLP_REJECT` reader - sleep reject interrupt raw"]
6pub type SLP_REJECT_R = crate::BitReader;
7#[doc = "Field `WDT` reader - RTC WDT interrupt raw"]
8pub type WDT_R = crate::BitReader;
9#[doc = "Field `BROWN_OUT` reader - brown out interrupt raw"]
10pub type BROWN_OUT_R = crate::BitReader;
11#[doc = "Field `MAIN_TIMER` reader - RTC main timer interrupt raw"]
12pub type MAIN_TIMER_R = crate::BitReader;
13#[doc = "Field `SWD` reader - super watch dog interrupt raw"]
14pub type SWD_R = crate::BitReader;
15#[doc = "Field `XTAL32K_DEAD` reader - xtal32k dead detection interrupt raw"]
16pub type XTAL32K_DEAD_R = crate::BitReader;
17#[doc = "Field `GLITCH_DET` reader - glitch_det_interrupt_raw"]
18pub type GLITCH_DET_R = crate::BitReader;
19#[doc = "Field `BBPLL_CAL` reader - bbpll cal end interrupt state"]
20pub type BBPLL_CAL_R = crate::BitReader;
21impl R {
22    #[doc = "Bit 0 - sleep wakeup interrupt raw"]
23    #[inline(always)]
24    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
25        SLP_WAKEUP_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - sleep reject interrupt raw"]
28    #[inline(always)]
29    pub fn slp_reject(&self) -> SLP_REJECT_R {
30        SLP_REJECT_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 3 - RTC WDT interrupt raw"]
33    #[inline(always)]
34    pub fn wdt(&self) -> WDT_R {
35        WDT_R::new(((self.bits >> 3) & 1) != 0)
36    }
37    #[doc = "Bit 9 - brown out interrupt raw"]
38    #[inline(always)]
39    pub fn brown_out(&self) -> BROWN_OUT_R {
40        BROWN_OUT_R::new(((self.bits >> 9) & 1) != 0)
41    }
42    #[doc = "Bit 10 - RTC main timer interrupt raw"]
43    #[inline(always)]
44    pub fn main_timer(&self) -> MAIN_TIMER_R {
45        MAIN_TIMER_R::new(((self.bits >> 10) & 1) != 0)
46    }
47    #[doc = "Bit 15 - super watch dog interrupt raw"]
48    #[inline(always)]
49    pub fn swd(&self) -> SWD_R {
50        SWD_R::new(((self.bits >> 15) & 1) != 0)
51    }
52    #[doc = "Bit 16 - xtal32k dead detection interrupt raw"]
53    #[inline(always)]
54    pub fn xtal32k_dead(&self) -> XTAL32K_DEAD_R {
55        XTAL32K_DEAD_R::new(((self.bits >> 16) & 1) != 0)
56    }
57    #[doc = "Bit 19 - glitch_det_interrupt_raw"]
58    #[inline(always)]
59    pub fn glitch_det(&self) -> GLITCH_DET_R {
60        GLITCH_DET_R::new(((self.bits >> 19) & 1) != 0)
61    }
62    #[doc = "Bit 20 - bbpll cal end interrupt state"]
63    #[inline(always)]
64    pub fn bbpll_cal(&self) -> BBPLL_CAL_R {
65        BBPLL_CAL_R::new(((self.bits >> 20) & 1) != 0)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("INT_RAW")
72            .field("slp_wakeup", &self.slp_wakeup())
73            .field("slp_reject", &self.slp_reject())
74            .field("wdt", &self.wdt())
75            .field("brown_out", &self.brown_out())
76            .field("main_timer", &self.main_timer())
77            .field("swd", &self.swd())
78            .field("xtal32k_dead", &self.xtal32k_dead())
79            .field("glitch_det", &self.glitch_det())
80            .field("bbpll_cal", &self.bbpll_cal())
81            .finish()
82    }
83}
84#[doc = "rtc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct INT_RAW_SPEC;
86impl crate::RegisterSpec for INT_RAW_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
90impl crate::Readable for INT_RAW_SPEC {}
91#[doc = "`reset()` method sets INT_RAW to value 0"]
92impl crate::Resettable for INT_RAW_SPEC {
93    const RESET_VALUE: u32 = 0;
94}
esp32c3/rtc_cntl/int_raw.rs

esp32c3/rtc_cntl/
int_raw.rs
