1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `RXFIFO_WM` reader - reg_rxfifo_wm_int_raw"]
4pub type RXFIFO_WM_R = crate::BitReader;
5#[doc = "Field `TXFIFO_WM` reader - reg_txfifo_wm_int_raw"]
6pub type TXFIFO_WM_R = crate::BitReader;
7#[doc = "Field `RXFIFO_OVF` reader - reg_rxfifo_ovf_int_raw"]
8pub type RXFIFO_OVF_R = crate::BitReader;
9#[doc = "Field `END_DETECT` reader - reg_end_detect_int_raw"]
10pub type END_DETECT_R = crate::BitReader;
11#[doc = "Field `BYTE_TRANS_DONE` reader - reg_byte_trans_done_int_raw"]
12pub type BYTE_TRANS_DONE_R = crate::BitReader;
13#[doc = "Field `ARBITRATION_LOST` reader - reg_arbitration_lost_int_raw"]
14pub type ARBITRATION_LOST_R = crate::BitReader;
15#[doc = "Field `MST_TXFIFO_UDF` reader - reg_mst_txfifo_udf_int_raw"]
16pub type MST_TXFIFO_UDF_R = crate::BitReader;
17#[doc = "Field `TRANS_COMPLETE` reader - reg_trans_complete_int_raw"]
18pub type TRANS_COMPLETE_R = crate::BitReader;
19#[doc = "Field `TIME_OUT` reader - reg_time_out_int_raw"]
20pub type TIME_OUT_R = crate::BitReader;
21#[doc = "Field `TRANS_START` reader - reg_trans_start_int_raw"]
22pub type TRANS_START_R = crate::BitReader;
23#[doc = "Field `NACK` reader - reg_nack_int_raw"]
24pub type NACK_R = crate::BitReader;
25#[doc = "Field `TXFIFO_OVF` reader - reg_txfifo_ovf_int_raw"]
26pub type TXFIFO_OVF_R = crate::BitReader;
27#[doc = "Field `RXFIFO_UDF` reader - reg_rxfifo_udf_int_raw"]
28pub type RXFIFO_UDF_R = crate::BitReader;
29#[doc = "Field `SCL_ST_TO` reader - reg_scl_st_to_int_raw"]
30pub type SCL_ST_TO_R = crate::BitReader;
31#[doc = "Field `SCL_MAIN_ST_TO` reader - reg_scl_main_st_to_int_raw"]
32pub type SCL_MAIN_ST_TO_R = crate::BitReader;
33#[doc = "Field `DET_START` reader - reg_det_start_int_raw"]
34pub type DET_START_R = crate::BitReader;
35#[doc = "Field `SLAVE_STRETCH` reader - reg_slave_stretch_int_raw"]
36pub type SLAVE_STRETCH_R = crate::BitReader;
37#[doc = "Field `GENERAL_CALL` reader - reg_general_call_int_raw"]
38pub type GENERAL_CALL_R = crate::BitReader;
39impl R {
40 #[doc = "Bit 0 - reg_rxfifo_wm_int_raw"]
41 #[inline(always)]
42 pub fn rxfifo_wm(&self) -> RXFIFO_WM_R {
43 RXFIFO_WM_R::new((self.bits & 1) != 0)
44 }
45 #[doc = "Bit 1 - reg_txfifo_wm_int_raw"]
46 #[inline(always)]
47 pub fn txfifo_wm(&self) -> TXFIFO_WM_R {
48 TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0)
49 }
50 #[doc = "Bit 2 - reg_rxfifo_ovf_int_raw"]
51 #[inline(always)]
52 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
53 RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0)
54 }
55 #[doc = "Bit 3 - reg_end_detect_int_raw"]
56 #[inline(always)]
57 pub fn end_detect(&self) -> END_DETECT_R {
58 END_DETECT_R::new(((self.bits >> 3) & 1) != 0)
59 }
60 #[doc = "Bit 4 - reg_byte_trans_done_int_raw"]
61 #[inline(always)]
62 pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R {
63 BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0)
64 }
65 #[doc = "Bit 5 - reg_arbitration_lost_int_raw"]
66 #[inline(always)]
67 pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
68 ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
69 }
70 #[doc = "Bit 6 - reg_mst_txfifo_udf_int_raw"]
71 #[inline(always)]
72 pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R {
73 MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0)
74 }
75 #[doc = "Bit 7 - reg_trans_complete_int_raw"]
76 #[inline(always)]
77 pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
78 TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
79 }
80 #[doc = "Bit 8 - reg_time_out_int_raw"]
81 #[inline(always)]
82 pub fn time_out(&self) -> TIME_OUT_R {
83 TIME_OUT_R::new(((self.bits >> 8) & 1) != 0)
84 }
85 #[doc = "Bit 9 - reg_trans_start_int_raw"]
86 #[inline(always)]
87 pub fn trans_start(&self) -> TRANS_START_R {
88 TRANS_START_R::new(((self.bits >> 9) & 1) != 0)
89 }
90 #[doc = "Bit 10 - reg_nack_int_raw"]
91 #[inline(always)]
92 pub fn nack(&self) -> NACK_R {
93 NACK_R::new(((self.bits >> 10) & 1) != 0)
94 }
95 #[doc = "Bit 11 - reg_txfifo_ovf_int_raw"]
96 #[inline(always)]
97 pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R {
98 TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0)
99 }
100 #[doc = "Bit 12 - reg_rxfifo_udf_int_raw"]
101 #[inline(always)]
102 pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R {
103 RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0)
104 }
105 #[doc = "Bit 13 - reg_scl_st_to_int_raw"]
106 #[inline(always)]
107 pub fn scl_st_to(&self) -> SCL_ST_TO_R {
108 SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0)
109 }
110 #[doc = "Bit 14 - reg_scl_main_st_to_int_raw"]
111 #[inline(always)]
112 pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R {
113 SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0)
114 }
115 #[doc = "Bit 15 - reg_det_start_int_raw"]
116 #[inline(always)]
117 pub fn det_start(&self) -> DET_START_R {
118 DET_START_R::new(((self.bits >> 15) & 1) != 0)
119 }
120 #[doc = "Bit 16 - reg_slave_stretch_int_raw"]
121 #[inline(always)]
122 pub fn slave_stretch(&self) -> SLAVE_STRETCH_R {
123 SLAVE_STRETCH_R::new(((self.bits >> 16) & 1) != 0)
124 }
125 #[doc = "Bit 17 - reg_general_call_int_raw"]
126 #[inline(always)]
127 pub fn general_call(&self) -> GENERAL_CALL_R {
128 GENERAL_CALL_R::new(((self.bits >> 17) & 1) != 0)
129 }
130}
131#[cfg(feature = "impl-register-debug")]
132impl core::fmt::Debug for R {
133 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
134 f.debug_struct("INT_RAW")
135 .field("rxfifo_wm", &self.rxfifo_wm())
136 .field("txfifo_wm", &self.txfifo_wm())
137 .field("rxfifo_ovf", &self.rxfifo_ovf())
138 .field("end_detect", &self.end_detect())
139 .field("byte_trans_done", &self.byte_trans_done())
140 .field("arbitration_lost", &self.arbitration_lost())
141 .field("mst_txfifo_udf", &self.mst_txfifo_udf())
142 .field("trans_complete", &self.trans_complete())
143 .field("time_out", &self.time_out())
144 .field("trans_start", &self.trans_start())
145 .field("nack", &self.nack())
146 .field("txfifo_ovf", &self.txfifo_ovf())
147 .field("rxfifo_udf", &self.rxfifo_udf())
148 .field("scl_st_to", &self.scl_st_to())
149 .field("scl_main_st_to", &self.scl_main_st_to())
150 .field("det_start", &self.det_start())
151 .field("slave_stretch", &self.slave_stretch())
152 .field("general_call", &self.general_call())
153 .finish()
154 }
155}
156#[doc = "I2C_INT_RAW_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
157pub struct INT_RAW_SPEC;
158impl crate::RegisterSpec for INT_RAW_SPEC {
159 type Ux = u32;
160}
161#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
162impl crate::Readable for INT_RAW_SPEC {}
163#[doc = "`reset()` method sets INT_RAW to value 0x02"]
164impl crate::Resettable for INT_RAW_SPEC {
165 const RESET_VALUE: u32 = 0x02;
166}