esp32c3/extmem/
cache_sync_int_ctrl.rs

1#[doc = "Register `CACHE_SYNC_INT_CTRL` reader"]
2pub type R = crate::R<CACHE_SYNC_INT_CTRL_SPEC>;
3#[doc = "Register `CACHE_SYNC_INT_CTRL` writer"]
4pub type W = crate::W<CACHE_SYNC_INT_CTRL_SPEC>;
5#[doc = "Field `ST` reader - The bit is used to indicate the interrupt by icache sync done."]
6pub type ST_R = crate::BitReader;
7#[doc = "Field `ENA` reader - The bit is used to enable the interrupt by icache sync done."]
8pub type ENA_R = crate::BitReader;
9#[doc = "Field `ENA` writer - The bit is used to enable the interrupt by icache sync done."]
10pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CLR` writer - The bit is used to clear the interrupt by icache sync done."]
12pub type CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - The bit is used to indicate the interrupt by icache sync done."]
15    #[inline(always)]
16    pub fn st(&self) -> ST_R {
17        ST_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
20    #[inline(always)]
21    pub fn ena(&self) -> ENA_R {
22        ENA_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CACHE_SYNC_INT_CTRL")
29            .field("st", &self.st())
30            .field("ena", &self.ena())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
36    #[inline(always)]
37    pub fn ena(&mut self) -> ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
38        ENA_W::new(self, 1)
39    }
40    #[doc = "Bit 2 - The bit is used to clear the interrupt by icache sync done."]
41    #[inline(always)]
42    pub fn clr(&mut self) -> CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
43        CLR_W::new(self, 2)
44    }
45}
46#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sync_int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sync_int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CACHE_SYNC_INT_CTRL_SPEC;
48impl crate::RegisterSpec for CACHE_SYNC_INT_CTRL_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`cache_sync_int_ctrl::R`](R) reader structure"]
52impl crate::Readable for CACHE_SYNC_INT_CTRL_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`cache_sync_int_ctrl::W`](W) writer structure"]
54impl crate::Writable for CACHE_SYNC_INT_CTRL_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x04;
58}
59#[doc = "`reset()` method sets CACHE_SYNC_INT_CTRL to value 0"]
60impl crate::Resettable for CACHE_SYNC_INT_CTRL_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32c3/extmem/cache_sync_int_ctrl.rs

esp32c3/extmem/
cache_sync_int_ctrl.rs
