esp32c3/extmem/
cache_state.rs

1#[doc = "Register `CACHE_STATE` reader"]
2pub type R = crate::R<CACHE_STATE_SPEC>;
3#[doc = "Field `ICACHE_STATE` reader - The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state"]
4pub type ICACHE_STATE_R = crate::FieldReader<u16>;
5impl R {
6    #[doc = "Bits 0:11 - The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state"]
7    #[inline(always)]
8    pub fn icache_state(&self) -> ICACHE_STATE_R {
9        ICACHE_STATE_R::new((self.bits & 0x0fff) as u16)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("CACHE_STATE")
16            .field("icache_state", &self.icache_state())
17            .finish()
18    }
19}
20#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct CACHE_STATE_SPEC;
22impl crate::RegisterSpec for CACHE_STATE_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`cache_state::R`](R) reader structure"]
26impl crate::Readable for CACHE_STATE_SPEC {}
27#[doc = "`reset()` method sets CACHE_STATE to value 0x01"]
28impl crate::Resettable for CACHE_STATE_SPEC {
29    const RESET_VALUE: u32 = 0x01;
30}
esp32c3/extmem/cache_state.rs

esp32c3/extmem/
cache_state.rs
