Module spi0

Source
Expand description

SPI (Serial Peripheral Interface) Controller 0

Modules§

cache_fctrl
SPI0 bit mode control register.
clock
SPI clock division control register.
clock_gate
SPI0 clk_gate register
core_clk_sel
SPI0 module clock select register
ctrl
SPI0 control register.
ctrl1
SPI0 control1 register.
ctrl2
SPI0 control2 register.
date
Version control register
din_mode
SPI0 input delay mode control register
din_num
SPI0 input delay number control register
dout_mode
SPI0 output delay mode control register
fsm
SPI0 FSM status register
misc
SPI0 misc register
rd_status
SPI0 read control register.
timing_cali
SPI0 timing calibration register
user
SPI0 user register.
user1
SPI0 user1 register.
user2
SPI0 user2 register.

Structs§

RegisterBlock
Register block

Type Aliases§

CACHE_FCTRL
CACHE_FCTRL (rw) register accessor: SPI0 bit mode control register.
CLOCK
CLOCK (rw) register accessor: SPI clock division control register.
CLOCK_GATE
CLOCK_GATE (rw) register accessor: SPI0 clk_gate register
CORE_CLK_SEL
CORE_CLK_SEL (rw) register accessor: SPI0 module clock select register
CTRL
CTRL (rw) register accessor: SPI0 control register.
CTRL1
CTRL1 (rw) register accessor: SPI0 control1 register.
CTRL2
CTRL2 (rw) register accessor: SPI0 control2 register.
DATE
DATE (rw) register accessor: Version control register
DIN_MODE
DIN_MODE (rw) register accessor: SPI0 input delay mode control register
DIN_NUM
DIN_NUM (rw) register accessor: SPI0 input delay number control register
DOUT_MODE
DOUT_MODE (rw) register accessor: SPI0 output delay mode control register
FSM
FSM (rw) register accessor: SPI0 FSM status register
MISC
MISC (rw) register accessor: SPI0 misc register
RD_STATUS
RD_STATUS (rw) register accessor: SPI0 read control register.
TIMING_CALI
TIMING_CALI (rw) register accessor: SPI0 timing calibration register
USER
USER (rw) register accessor: SPI0 user register.
USER1
USER1 (rw) register accessor: SPI0 user1 register.
USER2
USER2 (rw) register accessor: SPI0 user2 register.