esp32c3/sensitive/
clock_gate.rs1#[doc = "Register `CLOCK_GATE` reader"]
2pub type R = crate::R<CLOCK_GATE_SPEC>;
3#[doc = "Register `CLOCK_GATE` writer"]
4pub type W = crate::W<CLOCK_GATE_SPEC>;
5#[doc = "Field `CLK_EN` reader - clk_en"]
6pub type CLK_EN_R = crate::BitReader;
7#[doc = "Field `CLK_EN` writer - clk_en"]
8pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10 #[doc = "Bit 0 - clk_en"]
11 #[inline(always)]
12 pub fn clk_en(&self) -> CLK_EN_R {
13 CLK_EN_R::new((self.bits & 1) != 0)
14 }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19 f.debug_struct("CLOCK_GATE")
20 .field("clk_en", &self.clk_en())
21 .finish()
22 }
23}
24impl W {
25 #[doc = "Bit 0 - clk_en"]
26 #[inline(always)]
27 pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
28 CLK_EN_W::new(self, 0)
29 }
30}
31#[doc = "SENSITIVE_CLOCK_GATE_REG_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct CLOCK_GATE_SPEC;
33impl crate::RegisterSpec for CLOCK_GATE_SPEC {
34 type Ux = u32;
35}
36#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
37impl crate::Readable for CLOCK_GATE_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
39impl crate::Writable for CLOCK_GATE_SPEC {
40 type Safety = crate::Unsafe;
41 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"]
45impl crate::Resettable for CLOCK_GATE_SPEC {
46 const RESET_VALUE: u32 = 0x01;
47}