Expand description
SPI1 interrupt raw register
Structs§
- INT_
RAW_ SPEC - SPI1 interrupt raw register
Type Aliases§
- MST_
ST_ END_ R - Field
MST_ST_END
reader - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. - MST_
ST_ END_ W - Field
MST_ST_END
writer - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. - PER_
END_ R - Field
PER_END
reader - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. - PER_
END_ W - Field
PER_END
writer - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. - PES_
END_ R - Field
PES_END
reader - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. - PES_
END_ W - Field
PES_END
writer - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. - R
- Register
INT_RAW
reader - SLV_
ST_ END_ R - Field
SLV_ST_END
reader - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others - SLV_
ST_ END_ W - Field
SLV_ST_END
writer - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others - W
- Register
INT_RAW
writer - WPE_
END_ R - Field
WPE_END
reader - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. - WPE_
END_ W - Field
WPE_END
writer - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.