1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode."]
6pub type PARITY_R = crate::BitReader;
7#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode."]
8pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."]
10pub type PARITY_EN_R = crate::BitReader;
11#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."]
12pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `BIT_NUM` reader - This register is used to set the length of data."]
14pub type BIT_NUM_R = crate::FieldReader;
15#[doc = "Field `BIT_NUM` writer - This register is used to set the length of data."]
16pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit."]
18pub type STOP_BIT_NUM_R = crate::FieldReader;
19#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit."]
20pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."]
22pub type SW_RTS_R = crate::BitReader;
23#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."]
24pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SW_DTR` reader - This register is used to configure the software dtr signal which is used in software flow control."]
26pub type SW_DTR_R = crate::BitReader;
27#[doc = "Field `SW_DTR` writer - This register is used to configure the software dtr signal which is used in software flow control."]
28pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
30pub type TXD_BRK_R = crate::BitReader;
31#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
32pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IRDA_DPLX` reader - Set this bit to enable IrDA loopback mode."]
34pub type IRDA_DPLX_R = crate::BitReader;
35#[doc = "Field `IRDA_DPLX` writer - Set this bit to enable IrDA loopback mode."]
36pub type IRDA_DPLX_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `IRDA_TX_EN` reader - This is the start enable bit for IrDA transmitter."]
38pub type IRDA_TX_EN_R = crate::BitReader;
39#[doc = "Field `IRDA_TX_EN` writer - This is the start enable bit for IrDA transmitter."]
40pub type IRDA_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `IRDA_WCTL` reader - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
42pub type IRDA_WCTL_R = crate::BitReader;
43#[doc = "Field `IRDA_WCTL` writer - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
44pub type IRDA_WCTL_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `IRDA_TX_INV` reader - Set this bit to invert the level of IrDA transmitter."]
46pub type IRDA_TX_INV_R = crate::BitReader;
47#[doc = "Field `IRDA_TX_INV` writer - Set this bit to invert the level of IrDA transmitter."]
48pub type IRDA_TX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `IRDA_RX_INV` reader - Set this bit to invert the level of IrDA receiver."]
50pub type IRDA_RX_INV_R = crate::BitReader;
51#[doc = "Field `IRDA_RX_INV` writer - Set this bit to invert the level of IrDA receiver."]
52pub type IRDA_RX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."]
54pub type LOOPBACK_R = crate::BitReader;
55#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."]
56pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable flow control function for transmitter."]
58pub type TX_FLOW_EN_R = crate::BitReader;
59#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable flow control function for transmitter."]
60pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `IRDA_EN` reader - Set this bit to enable IrDA protocol."]
62pub type IRDA_EN_R = crate::BitReader;
63#[doc = "Field `IRDA_EN` writer - Set this bit to enable IrDA protocol."]
64pub type IRDA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset the uart receive-FIFO."]
66pub type RXFIFO_RST_R = crate::BitReader;
67#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset the uart receive-FIFO."]
68pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset the uart transmit-FIFO."]
70pub type TXFIFO_RST_R = crate::BitReader;
71#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset the uart transmit-FIFO."]
72pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."]
74pub type RXD_INV_R = crate::BitReader;
75#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."]
76pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CTS_INV` reader - Set this bit to inverse the level value of uart cts signal."]
78pub type CTS_INV_R = crate::BitReader;
79#[doc = "Field `CTS_INV` writer - Set this bit to inverse the level value of uart cts signal."]
80pub type CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `DSR_INV` reader - Set this bit to inverse the level value of uart dsr signal."]
82pub type DSR_INV_R = crate::BitReader;
83#[doc = "Field `DSR_INV` writer - Set this bit to inverse the level value of uart dsr signal."]
84pub type DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."]
86pub type TXD_INV_R = crate::BitReader;
87#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."]
88pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `RTS_INV` reader - Set this bit to inverse the level value of uart rts signal."]
90pub type RTS_INV_R = crate::BitReader;
91#[doc = "Field `RTS_INV` writer - Set this bit to inverse the level value of uart rts signal."]
92pub type RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `DTR_INV` reader - Set this bit to inverse the level value of uart dtr signal."]
94pub type DTR_INV_R = crate::BitReader;
95#[doc = "Field `DTR_INV` writer - Set this bit to inverse the level value of uart dtr signal."]
96pub type DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
98pub type CLK_EN_R = crate::BitReader;
99#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
100pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `ERR_WR_MASK` reader - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
102pub type ERR_WR_MASK_R = crate::BitReader;
103#[doc = "Field `ERR_WR_MASK` writer - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
104pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `AUTOBAUD_EN` reader - This is the enable bit for detecting baudrate."]
106pub type AUTOBAUD_EN_R = crate::BitReader;
107#[doc = "Field `AUTOBAUD_EN` writer - This is the enable bit for detecting baudrate."]
108pub type AUTOBAUD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `MEM_CLK_EN` reader - UART memory clock gate enable signal."]
110pub type MEM_CLK_EN_R = crate::BitReader;
111#[doc = "Field `MEM_CLK_EN` writer - UART memory clock gate enable signal."]
112pub type MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
113impl R {
114 #[doc = "Bit 0 - This register is used to configure the parity check mode."]
115 #[inline(always)]
116 pub fn parity(&self) -> PARITY_R {
117 PARITY_R::new((self.bits & 1) != 0)
118 }
119 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
120 #[inline(always)]
121 pub fn parity_en(&self) -> PARITY_EN_R {
122 PARITY_EN_R::new(((self.bits >> 1) & 1) != 0)
123 }
124 #[doc = "Bits 2:3 - This register is used to set the length of data."]
125 #[inline(always)]
126 pub fn bit_num(&self) -> BIT_NUM_R {
127 BIT_NUM_R::new(((self.bits >> 2) & 3) as u8)
128 }
129 #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
130 #[inline(always)]
131 pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R {
132 STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8)
133 }
134 #[doc = "Bit 6 - This register is used to configure the software rts signal which is used in software flow control."]
135 #[inline(always)]
136 pub fn sw_rts(&self) -> SW_RTS_R {
137 SW_RTS_R::new(((self.bits >> 6) & 1) != 0)
138 }
139 #[doc = "Bit 7 - This register is used to configure the software dtr signal which is used in software flow control."]
140 #[inline(always)]
141 pub fn sw_dtr(&self) -> SW_DTR_R {
142 SW_DTR_R::new(((self.bits >> 7) & 1) != 0)
143 }
144 #[doc = "Bit 8 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
145 #[inline(always)]
146 pub fn txd_brk(&self) -> TXD_BRK_R {
147 TXD_BRK_R::new(((self.bits >> 8) & 1) != 0)
148 }
149 #[doc = "Bit 9 - Set this bit to enable IrDA loopback mode."]
150 #[inline(always)]
151 pub fn irda_dplx(&self) -> IRDA_DPLX_R {
152 IRDA_DPLX_R::new(((self.bits >> 9) & 1) != 0)
153 }
154 #[doc = "Bit 10 - This is the start enable bit for IrDA transmitter."]
155 #[inline(always)]
156 pub fn irda_tx_en(&self) -> IRDA_TX_EN_R {
157 IRDA_TX_EN_R::new(((self.bits >> 10) & 1) != 0)
158 }
159 #[doc = "Bit 11 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
160 #[inline(always)]
161 pub fn irda_wctl(&self) -> IRDA_WCTL_R {
162 IRDA_WCTL_R::new(((self.bits >> 11) & 1) != 0)
163 }
164 #[doc = "Bit 12 - Set this bit to invert the level of IrDA transmitter."]
165 #[inline(always)]
166 pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R {
167 IRDA_TX_INV_R::new(((self.bits >> 12) & 1) != 0)
168 }
169 #[doc = "Bit 13 - Set this bit to invert the level of IrDA receiver."]
170 #[inline(always)]
171 pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R {
172 IRDA_RX_INV_R::new(((self.bits >> 13) & 1) != 0)
173 }
174 #[doc = "Bit 14 - Set this bit to enable uart loopback test mode."]
175 #[inline(always)]
176 pub fn loopback(&self) -> LOOPBACK_R {
177 LOOPBACK_R::new(((self.bits >> 14) & 1) != 0)
178 }
179 #[doc = "Bit 15 - Set this bit to enable flow control function for transmitter."]
180 #[inline(always)]
181 pub fn tx_flow_en(&self) -> TX_FLOW_EN_R {
182 TX_FLOW_EN_R::new(((self.bits >> 15) & 1) != 0)
183 }
184 #[doc = "Bit 16 - Set this bit to enable IrDA protocol."]
185 #[inline(always)]
186 pub fn irda_en(&self) -> IRDA_EN_R {
187 IRDA_EN_R::new(((self.bits >> 16) & 1) != 0)
188 }
189 #[doc = "Bit 17 - Set this bit to reset the uart receive-FIFO."]
190 #[inline(always)]
191 pub fn rxfifo_rst(&self) -> RXFIFO_RST_R {
192 RXFIFO_RST_R::new(((self.bits >> 17) & 1) != 0)
193 }
194 #[doc = "Bit 18 - Set this bit to reset the uart transmit-FIFO."]
195 #[inline(always)]
196 pub fn txfifo_rst(&self) -> TXFIFO_RST_R {
197 TXFIFO_RST_R::new(((self.bits >> 18) & 1) != 0)
198 }
199 #[doc = "Bit 19 - Set this bit to inverse the level value of uart rxd signal."]
200 #[inline(always)]
201 pub fn rxd_inv(&self) -> RXD_INV_R {
202 RXD_INV_R::new(((self.bits >> 19) & 1) != 0)
203 }
204 #[doc = "Bit 20 - Set this bit to inverse the level value of uart cts signal."]
205 #[inline(always)]
206 pub fn cts_inv(&self) -> CTS_INV_R {
207 CTS_INV_R::new(((self.bits >> 20) & 1) != 0)
208 }
209 #[doc = "Bit 21 - Set this bit to inverse the level value of uart dsr signal."]
210 #[inline(always)]
211 pub fn dsr_inv(&self) -> DSR_INV_R {
212 DSR_INV_R::new(((self.bits >> 21) & 1) != 0)
213 }
214 #[doc = "Bit 22 - Set this bit to inverse the level value of uart txd signal."]
215 #[inline(always)]
216 pub fn txd_inv(&self) -> TXD_INV_R {
217 TXD_INV_R::new(((self.bits >> 22) & 1) != 0)
218 }
219 #[doc = "Bit 23 - Set this bit to inverse the level value of uart rts signal."]
220 #[inline(always)]
221 pub fn rts_inv(&self) -> RTS_INV_R {
222 RTS_INV_R::new(((self.bits >> 23) & 1) != 0)
223 }
224 #[doc = "Bit 24 - Set this bit to inverse the level value of uart dtr signal."]
225 #[inline(always)]
226 pub fn dtr_inv(&self) -> DTR_INV_R {
227 DTR_INV_R::new(((self.bits >> 24) & 1) != 0)
228 }
229 #[doc = "Bit 25 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
230 #[inline(always)]
231 pub fn clk_en(&self) -> CLK_EN_R {
232 CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
233 }
234 #[doc = "Bit 26 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
235 #[inline(always)]
236 pub fn err_wr_mask(&self) -> ERR_WR_MASK_R {
237 ERR_WR_MASK_R::new(((self.bits >> 26) & 1) != 0)
238 }
239 #[doc = "Bit 27 - This is the enable bit for detecting baudrate."]
240 #[inline(always)]
241 pub fn autobaud_en(&self) -> AUTOBAUD_EN_R {
242 AUTOBAUD_EN_R::new(((self.bits >> 27) & 1) != 0)
243 }
244 #[doc = "Bit 28 - UART memory clock gate enable signal."]
245 #[inline(always)]
246 pub fn mem_clk_en(&self) -> MEM_CLK_EN_R {
247 MEM_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
248 }
249}
250#[cfg(feature = "impl-register-debug")]
251impl core::fmt::Debug for R {
252 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
253 f.debug_struct("CONF0")
254 .field("parity", &self.parity())
255 .field("parity_en", &self.parity_en())
256 .field("bit_num", &self.bit_num())
257 .field("stop_bit_num", &self.stop_bit_num())
258 .field("sw_rts", &self.sw_rts())
259 .field("sw_dtr", &self.sw_dtr())
260 .field("txd_brk", &self.txd_brk())
261 .field("irda_dplx", &self.irda_dplx())
262 .field("irda_tx_en", &self.irda_tx_en())
263 .field("irda_wctl", &self.irda_wctl())
264 .field("irda_tx_inv", &self.irda_tx_inv())
265 .field("irda_rx_inv", &self.irda_rx_inv())
266 .field("loopback", &self.loopback())
267 .field("tx_flow_en", &self.tx_flow_en())
268 .field("irda_en", &self.irda_en())
269 .field("rxfifo_rst", &self.rxfifo_rst())
270 .field("txfifo_rst", &self.txfifo_rst())
271 .field("rxd_inv", &self.rxd_inv())
272 .field("cts_inv", &self.cts_inv())
273 .field("dsr_inv", &self.dsr_inv())
274 .field("txd_inv", &self.txd_inv())
275 .field("rts_inv", &self.rts_inv())
276 .field("dtr_inv", &self.dtr_inv())
277 .field("clk_en", &self.clk_en())
278 .field("err_wr_mask", &self.err_wr_mask())
279 .field("autobaud_en", &self.autobaud_en())
280 .field("mem_clk_en", &self.mem_clk_en())
281 .finish()
282 }
283}
284impl W {
285 #[doc = "Bit 0 - This register is used to configure the parity check mode."]
286 #[inline(always)]
287 pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
288 PARITY_W::new(self, 0)
289 }
290 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
291 #[inline(always)]
292 pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
293 PARITY_EN_W::new(self, 1)
294 }
295 #[doc = "Bits 2:3 - This register is used to set the length of data."]
296 #[inline(always)]
297 pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
298 BIT_NUM_W::new(self, 2)
299 }
300 #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
301 #[inline(always)]
302 pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
303 STOP_BIT_NUM_W::new(self, 4)
304 }
305 #[doc = "Bit 6 - This register is used to configure the software rts signal which is used in software flow control."]
306 #[inline(always)]
307 pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
308 SW_RTS_W::new(self, 6)
309 }
310 #[doc = "Bit 7 - This register is used to configure the software dtr signal which is used in software flow control."]
311 #[inline(always)]
312 pub fn sw_dtr(&mut self) -> SW_DTR_W<CONF0_SPEC> {
313 SW_DTR_W::new(self, 7)
314 }
315 #[doc = "Bit 8 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
316 #[inline(always)]
317 pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
318 TXD_BRK_W::new(self, 8)
319 }
320 #[doc = "Bit 9 - Set this bit to enable IrDA loopback mode."]
321 #[inline(always)]
322 pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
323 IRDA_DPLX_W::new(self, 9)
324 }
325 #[doc = "Bit 10 - This is the start enable bit for IrDA transmitter."]
326 #[inline(always)]
327 pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
328 IRDA_TX_EN_W::new(self, 10)
329 }
330 #[doc = "Bit 11 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
331 #[inline(always)]
332 pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
333 IRDA_WCTL_W::new(self, 11)
334 }
335 #[doc = "Bit 12 - Set this bit to invert the level of IrDA transmitter."]
336 #[inline(always)]
337 pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
338 IRDA_TX_INV_W::new(self, 12)
339 }
340 #[doc = "Bit 13 - Set this bit to invert the level of IrDA receiver."]
341 #[inline(always)]
342 pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
343 IRDA_RX_INV_W::new(self, 13)
344 }
345 #[doc = "Bit 14 - Set this bit to enable uart loopback test mode."]
346 #[inline(always)]
347 pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
348 LOOPBACK_W::new(self, 14)
349 }
350 #[doc = "Bit 15 - Set this bit to enable flow control function for transmitter."]
351 #[inline(always)]
352 pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
353 TX_FLOW_EN_W::new(self, 15)
354 }
355 #[doc = "Bit 16 - Set this bit to enable IrDA protocol."]
356 #[inline(always)]
357 pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
358 IRDA_EN_W::new(self, 16)
359 }
360 #[doc = "Bit 17 - Set this bit to reset the uart receive-FIFO."]
361 #[inline(always)]
362 pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
363 RXFIFO_RST_W::new(self, 17)
364 }
365 #[doc = "Bit 18 - Set this bit to reset the uart transmit-FIFO."]
366 #[inline(always)]
367 pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
368 TXFIFO_RST_W::new(self, 18)
369 }
370 #[doc = "Bit 19 - Set this bit to inverse the level value of uart rxd signal."]
371 #[inline(always)]
372 pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
373 RXD_INV_W::new(self, 19)
374 }
375 #[doc = "Bit 20 - Set this bit to inverse the level value of uart cts signal."]
376 #[inline(always)]
377 pub fn cts_inv(&mut self) -> CTS_INV_W<CONF0_SPEC> {
378 CTS_INV_W::new(self, 20)
379 }
380 #[doc = "Bit 21 - Set this bit to inverse the level value of uart dsr signal."]
381 #[inline(always)]
382 pub fn dsr_inv(&mut self) -> DSR_INV_W<CONF0_SPEC> {
383 DSR_INV_W::new(self, 21)
384 }
385 #[doc = "Bit 22 - Set this bit to inverse the level value of uart txd signal."]
386 #[inline(always)]
387 pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
388 TXD_INV_W::new(self, 22)
389 }
390 #[doc = "Bit 23 - Set this bit to inverse the level value of uart rts signal."]
391 #[inline(always)]
392 pub fn rts_inv(&mut self) -> RTS_INV_W<CONF0_SPEC> {
393 RTS_INV_W::new(self, 23)
394 }
395 #[doc = "Bit 24 - Set this bit to inverse the level value of uart dtr signal."]
396 #[inline(always)]
397 pub fn dtr_inv(&mut self) -> DTR_INV_W<CONF0_SPEC> {
398 DTR_INV_W::new(self, 24)
399 }
400 #[doc = "Bit 25 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
401 #[inline(always)]
402 pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
403 CLK_EN_W::new(self, 25)
404 }
405 #[doc = "Bit 26 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
406 #[inline(always)]
407 pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
408 ERR_WR_MASK_W::new(self, 26)
409 }
410 #[doc = "Bit 27 - This is the enable bit for detecting baudrate."]
411 #[inline(always)]
412 pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W<CONF0_SPEC> {
413 AUTOBAUD_EN_W::new(self, 27)
414 }
415 #[doc = "Bit 28 - UART memory clock gate enable signal."]
416 #[inline(always)]
417 pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W<CONF0_SPEC> {
418 MEM_CLK_EN_W::new(self, 28)
419 }
420}
421#[doc = "a\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
422pub struct CONF0_SPEC;
423impl crate::RegisterSpec for CONF0_SPEC {
424 type Ux = u32;
425}
426#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
427impl crate::Readable for CONF0_SPEC {}
428#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
429impl crate::Writable for CONF0_SPEC {
430 type Safety = crate::Unsafe;
431 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
432 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
433}
434#[doc = "`reset()` method sets CONF0 to value 0x1000_001c"]
435impl crate::Resettable for CONF0_SPEC {
436 const RESET_VALUE: u32 = 0x1000_001c;
437}