esp32c2/timg0/t/
load.rs

1#[doc = "Register `LOAD` writer"]
2pub type W = crate::W<LOAD_SPEC>;
3#[doc = "Field `LOAD` writer - Write any value to trigger a timer %s time-base counter reload."]
4pub type LOAD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for crate::generic::Reg<LOAD_SPEC> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bits 0:31 - Write any value to trigger a timer %s time-base counter reload."]
13    #[inline(always)]
14    pub fn load(&mut self) -> LOAD_W<LOAD_SPEC> {
15        LOAD_W::new(self, 0)
16    }
17}
18#[doc = "Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct LOAD_SPEC;
20impl crate::RegisterSpec for LOAD_SPEC {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"]
24impl crate::Writable for LOAD_SPEC {
25    type Safety = crate::Unsafe;
26    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
27    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
28}
29#[doc = "`reset()` method sets LOAD to value 0"]
30impl crate::Resettable for LOAD_SPEC {
31    const RESET_VALUE: u32 = 0;
32}
esp32c2/timg0/t/load.rs

esp32c2/timg0/t/
load.rs
