1#[doc = "Register `SLAVE` reader"]
2pub type R = crate::R<SLAVE_SPEC>;
3#[doc = "Register `SLAVE` writer"]
4pub type W = crate::W<SLAVE_SPEC>;
5#[doc = "Field `CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
6pub type CLK_MODE_R = crate::FieldReader;
7#[doc = "Field `CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
8pub type CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CLK_MODE_13` reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
10pub type CLK_MODE_13_R = crate::BitReader;
11#[doc = "Field `CLK_MODE_13` writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
12pub type CLK_MODE_13_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RSCK_DATA_OUT` reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
14pub type RSCK_DATA_OUT_R = crate::BitReader;
15#[doc = "Field `RSCK_DATA_OUT` writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
16pub type RSCK_DATA_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_RDDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
18pub type SLV_RDDMA_BITLEN_EN_R = crate::BitReader;
19#[doc = "Field `SLV_RDDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
20pub type SLV_RDDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLV_WRDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
22pub type SLV_WRDMA_BITLEN_EN_R = crate::BitReader;
23#[doc = "Field `SLV_WRDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
24pub type SLV_WRDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLV_RDBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
26pub type SLV_RDBUF_BITLEN_EN_R = crate::BitReader;
27#[doc = "Field `SLV_RDBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
28pub type SLV_RDBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLV_WRBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
30pub type SLV_WRBUF_BITLEN_EN_R = crate::BitReader;
31#[doc = "Field `SLV_WRBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
32pub type SLV_WRBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DMA_SEG_MAGIC_VALUE` reader - The magic value of BM table in master DMA seg-trans."]
34pub type DMA_SEG_MAGIC_VALUE_R = crate::FieldReader;
35#[doc = "Field `DMA_SEG_MAGIC_VALUE` writer - The magic value of BM table in master DMA seg-trans."]
36pub type DMA_SEG_MAGIC_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37#[doc = "Field `MODE` reader - Set SPI work mode. 1: slave mode 0: master mode."]
38pub type MODE_R = crate::BitReader;
39#[doc = "Field `MODE` writer - Set SPI work mode. 1: slave mode 0: master mode."]
40pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SOFT_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
42pub type SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `USR_CONF` reader - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
44pub type USR_CONF_R = crate::BitReader;
45#[doc = "Field `USR_CONF` writer - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
46pub type USR_CONF_W<'a, REG> = crate::BitWriter<'a, REG>;
47impl R {
48 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
49 #[inline(always)]
50 pub fn clk_mode(&self) -> CLK_MODE_R {
51 CLK_MODE_R::new((self.bits & 3) as u8)
52 }
53 #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
54 #[inline(always)]
55 pub fn clk_mode_13(&self) -> CLK_MODE_13_R {
56 CLK_MODE_13_R::new(((self.bits >> 2) & 1) != 0)
57 }
58 #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
59 #[inline(always)]
60 pub fn rsck_data_out(&self) -> RSCK_DATA_OUT_R {
61 RSCK_DATA_OUT_R::new(((self.bits >> 3) & 1) != 0)
62 }
63 #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
64 #[inline(always)]
65 pub fn slv_rddma_bitlen_en(&self) -> SLV_RDDMA_BITLEN_EN_R {
66 SLV_RDDMA_BITLEN_EN_R::new(((self.bits >> 8) & 1) != 0)
67 }
68 #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
69 #[inline(always)]
70 pub fn slv_wrdma_bitlen_en(&self) -> SLV_WRDMA_BITLEN_EN_R {
71 SLV_WRDMA_BITLEN_EN_R::new(((self.bits >> 9) & 1) != 0)
72 }
73 #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
74 #[inline(always)]
75 pub fn slv_rdbuf_bitlen_en(&self) -> SLV_RDBUF_BITLEN_EN_R {
76 SLV_RDBUF_BITLEN_EN_R::new(((self.bits >> 10) & 1) != 0)
77 }
78 #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
79 #[inline(always)]
80 pub fn slv_wrbuf_bitlen_en(&self) -> SLV_WRBUF_BITLEN_EN_R {
81 SLV_WRBUF_BITLEN_EN_R::new(((self.bits >> 11) & 1) != 0)
82 }
83 #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
84 #[inline(always)]
85 pub fn dma_seg_magic_value(&self) -> DMA_SEG_MAGIC_VALUE_R {
86 DMA_SEG_MAGIC_VALUE_R::new(((self.bits >> 22) & 0x0f) as u8)
87 }
88 #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
89 #[inline(always)]
90 pub fn mode(&self) -> MODE_R {
91 MODE_R::new(((self.bits >> 26) & 1) != 0)
92 }
93 #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
94 #[inline(always)]
95 pub fn usr_conf(&self) -> USR_CONF_R {
96 USR_CONF_R::new(((self.bits >> 28) & 1) != 0)
97 }
98}
99#[cfg(feature = "impl-register-debug")]
100impl core::fmt::Debug for R {
101 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102 f.debug_struct("SLAVE")
103 .field("clk_mode", &self.clk_mode())
104 .field("clk_mode_13", &self.clk_mode_13())
105 .field("rsck_data_out", &self.rsck_data_out())
106 .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
107 .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
108 .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
109 .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
110 .field("dma_seg_magic_value", &self.dma_seg_magic_value())
111 .field("mode", &self.mode())
112 .field("usr_conf", &self.usr_conf())
113 .finish()
114 }
115}
116impl W {
117 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
118 #[inline(always)]
119 pub fn clk_mode(&mut self) -> CLK_MODE_W<SLAVE_SPEC> {
120 CLK_MODE_W::new(self, 0)
121 }
122 #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
123 #[inline(always)]
124 pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<SLAVE_SPEC> {
125 CLK_MODE_13_W::new(self, 2)
126 }
127 #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
128 #[inline(always)]
129 pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<SLAVE_SPEC> {
130 RSCK_DATA_OUT_W::new(self, 3)
131 }
132 #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
133 #[inline(always)]
134 pub fn slv_rddma_bitlen_en(&mut self) -> SLV_RDDMA_BITLEN_EN_W<SLAVE_SPEC> {
135 SLV_RDDMA_BITLEN_EN_W::new(self, 8)
136 }
137 #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
138 #[inline(always)]
139 pub fn slv_wrdma_bitlen_en(&mut self) -> SLV_WRDMA_BITLEN_EN_W<SLAVE_SPEC> {
140 SLV_WRDMA_BITLEN_EN_W::new(self, 9)
141 }
142 #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
143 #[inline(always)]
144 pub fn slv_rdbuf_bitlen_en(&mut self) -> SLV_RDBUF_BITLEN_EN_W<SLAVE_SPEC> {
145 SLV_RDBUF_BITLEN_EN_W::new(self, 10)
146 }
147 #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
148 #[inline(always)]
149 pub fn slv_wrbuf_bitlen_en(&mut self) -> SLV_WRBUF_BITLEN_EN_W<SLAVE_SPEC> {
150 SLV_WRBUF_BITLEN_EN_W::new(self, 11)
151 }
152 #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
153 #[inline(always)]
154 pub fn dma_seg_magic_value(&mut self) -> DMA_SEG_MAGIC_VALUE_W<SLAVE_SPEC> {
155 DMA_SEG_MAGIC_VALUE_W::new(self, 22)
156 }
157 #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
158 #[inline(always)]
159 pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
160 MODE_W::new(self, 26)
161 }
162 #[doc = "Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
163 #[inline(always)]
164 pub fn soft_reset(&mut self) -> SOFT_RESET_W<SLAVE_SPEC> {
165 SOFT_RESET_W::new(self, 27)
166 }
167 #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
168 #[inline(always)]
169 pub fn usr_conf(&mut self) -> USR_CONF_W<SLAVE_SPEC> {
170 USR_CONF_W::new(self, 28)
171 }
172}
173#[doc = "SPI slave control register\n\nYou can [`read`](crate::Reg::read) this register and get [`slave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
174pub struct SLAVE_SPEC;
175impl crate::RegisterSpec for SLAVE_SPEC {
176 type Ux = u32;
177}
178#[doc = "`read()` method returns [`slave::R`](R) reader structure"]
179impl crate::Readable for SLAVE_SPEC {}
180#[doc = "`write(|w| ..)` method takes [`slave::W`](W) writer structure"]
181impl crate::Writable for SLAVE_SPEC {
182 type Safety = crate::Unsafe;
183 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
184 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
185}
186#[doc = "`reset()` method sets SLAVE to value 0x0280_0000"]
187impl crate::Resettable for SLAVE_SPEC {
188 const RESET_VALUE: u32 = 0x0280_0000;
189}