esp32c2/spi2/
dout_mode.rs

1#[doc = "Register `DOUT_MODE` reader"]
2pub type R = crate::R<DOUT_MODE_SPEC>;
3#[doc = "Field `DOUT0_MODE` reader - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
4pub type DOUT0_MODE_R = crate::BitReader;
5#[doc = "Field `DOUT1_MODE` reader - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
6pub type DOUT1_MODE_R = crate::BitReader;
7#[doc = "Field `DOUT2_MODE` reader - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
8pub type DOUT2_MODE_R = crate::BitReader;
9#[doc = "Field `DOUT3_MODE` reader - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
10pub type DOUT3_MODE_R = crate::BitReader;
11#[doc = "Field `DOUT4_MODE` reader - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
12pub type DOUT4_MODE_R = crate::BitReader;
13#[doc = "Field `DOUT5_MODE` reader - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
14pub type DOUT5_MODE_R = crate::BitReader;
15#[doc = "Field `DOUT6_MODE` reader - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
16pub type DOUT6_MODE_R = crate::BitReader;
17#[doc = "Field `DOUT7_MODE` reader - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
18pub type DOUT7_MODE_R = crate::BitReader;
19#[doc = "Field `D_DQS_MODE` reader - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
20pub type D_DQS_MODE_R = crate::BitReader;
21impl R {
22    #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
23    #[inline(always)]
24    pub fn dout0_mode(&self) -> DOUT0_MODE_R {
25        DOUT0_MODE_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
28    #[inline(always)]
29    pub fn dout1_mode(&self) -> DOUT1_MODE_R {
30        DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
33    #[inline(always)]
34    pub fn dout2_mode(&self) -> DOUT2_MODE_R {
35        DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
38    #[inline(always)]
39    pub fn dout3_mode(&self) -> DOUT3_MODE_R {
40        DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0)
41    }
42    #[doc = "Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
43    #[inline(always)]
44    pub fn dout4_mode(&self) -> DOUT4_MODE_R {
45        DOUT4_MODE_R::new(((self.bits >> 4) & 1) != 0)
46    }
47    #[doc = "Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
48    #[inline(always)]
49    pub fn dout5_mode(&self) -> DOUT5_MODE_R {
50        DOUT5_MODE_R::new(((self.bits >> 5) & 1) != 0)
51    }
52    #[doc = "Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
53    #[inline(always)]
54    pub fn dout6_mode(&self) -> DOUT6_MODE_R {
55        DOUT6_MODE_R::new(((self.bits >> 6) & 1) != 0)
56    }
57    #[doc = "Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
58    #[inline(always)]
59    pub fn dout7_mode(&self) -> DOUT7_MODE_R {
60        DOUT7_MODE_R::new(((self.bits >> 7) & 1) != 0)
61    }
62    #[doc = "Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
63    #[inline(always)]
64    pub fn d_dqs_mode(&self) -> D_DQS_MODE_R {
65        D_DQS_MODE_R::new(((self.bits >> 8) & 1) != 0)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("DOUT_MODE")
72            .field("dout0_mode", &self.dout0_mode())
73            .field("dout1_mode", &self.dout1_mode())
74            .field("dout2_mode", &self.dout2_mode())
75            .field("dout3_mode", &self.dout3_mode())
76            .field("dout4_mode", &self.dout4_mode())
77            .field("dout5_mode", &self.dout5_mode())
78            .field("dout6_mode", &self.dout6_mode())
79            .field("dout7_mode", &self.dout7_mode())
80            .field("d_dqs_mode", &self.d_dqs_mode())
81            .finish()
82    }
83}
84#[doc = "SPI output delay mode configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`dout_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct DOUT_MODE_SPEC;
86impl crate::RegisterSpec for DOUT_MODE_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`dout_mode::R`](R) reader structure"]
90impl crate::Readable for DOUT_MODE_SPEC {}
91#[doc = "`reset()` method sets DOUT_MODE to value 0"]
92impl crate::Resettable for DOUT_MODE_SPEC {
93    const RESET_VALUE: u32 = 0;
94}
esp32c2/spi2/dout_mode.rs

esp32c2/spi2/
dout_mode.rs
