esp32c2/spi2/
dma_conf.rs

1#[doc = "Register `DMA_CONF` reader"]
2pub type R = crate::R<DMA_CONF_SPEC>;
3#[doc = "Register `DMA_CONF` writer"]
4pub type W = crate::W<DMA_CONF_SPEC>;
5#[doc = "Field `DMA_OUTFIFO_EMPTY` reader - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data."]
6pub type DMA_OUTFIFO_EMPTY_R = crate::BitReader;
7#[doc = "Field `DMA_INFIFO_FULL` reader - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data."]
8pub type DMA_INFIFO_FULL_R = crate::BitReader;
9#[doc = "Field `DMA_SLV_SEG_TRANS_EN` reader - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
10pub type DMA_SLV_SEG_TRANS_EN_R = crate::BitReader;
11#[doc = "Field `DMA_SLV_SEG_TRANS_EN` writer - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
12pub type DMA_SLV_SEG_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLV_RX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
14pub type SLV_RX_SEG_TRANS_CLR_EN_R = crate::BitReader;
15#[doc = "Field `SLV_RX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
16pub type SLV_RX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_TX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
18pub type SLV_TX_SEG_TRANS_CLR_EN_R = crate::BitReader;
19#[doc = "Field `SLV_TX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
20pub type SLV_TX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RX_EOF_EN` reader - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
22pub type RX_EOF_EN_R = crate::BitReader;
23#[doc = "Field `RX_EOF_EN` writer - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
24pub type RX_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DMA_RX_ENA` reader - Set this bit to enable SPI DMA controlled receive data mode."]
26pub type DMA_RX_ENA_R = crate::BitReader;
27#[doc = "Field `DMA_RX_ENA` writer - Set this bit to enable SPI DMA controlled receive data mode."]
28pub type DMA_RX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DMA_TX_ENA` reader - Set this bit to enable SPI DMA controlled send data mode."]
30pub type DMA_TX_ENA_R = crate::BitReader;
31#[doc = "Field `DMA_TX_ENA` writer - Set this bit to enable SPI DMA controlled send data mode."]
32pub type DMA_TX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RX_AFIFO_RST` writer - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."]
34pub type RX_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `BUF_AFIFO_RST` writer - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."]
36pub type BUF_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DMA_AFIFO_RST` writer - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."]
38pub type DMA_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
39impl R {
40    #[doc = "Bit 0 - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data."]
41    #[inline(always)]
42    pub fn dma_outfifo_empty(&self) -> DMA_OUTFIFO_EMPTY_R {
43        DMA_OUTFIFO_EMPTY_R::new((self.bits & 1) != 0)
44    }
45    #[doc = "Bit 1 - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data."]
46    #[inline(always)]
47    pub fn dma_infifo_full(&self) -> DMA_INFIFO_FULL_R {
48        DMA_INFIFO_FULL_R::new(((self.bits >> 1) & 1) != 0)
49    }
50    #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
51    #[inline(always)]
52    pub fn dma_slv_seg_trans_en(&self) -> DMA_SLV_SEG_TRANS_EN_R {
53        DMA_SLV_SEG_TRANS_EN_R::new(((self.bits >> 18) & 1) != 0)
54    }
55    #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
56    #[inline(always)]
57    pub fn slv_rx_seg_trans_clr_en(&self) -> SLV_RX_SEG_TRANS_CLR_EN_R {
58        SLV_RX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 19) & 1) != 0)
59    }
60    #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
61    #[inline(always)]
62    pub fn slv_tx_seg_trans_clr_en(&self) -> SLV_TX_SEG_TRANS_CLR_EN_R {
63        SLV_TX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 20) & 1) != 0)
64    }
65    #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
66    #[inline(always)]
67    pub fn rx_eof_en(&self) -> RX_EOF_EN_R {
68        RX_EOF_EN_R::new(((self.bits >> 21) & 1) != 0)
69    }
70    #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."]
71    #[inline(always)]
72    pub fn dma_rx_ena(&self) -> DMA_RX_ENA_R {
73        DMA_RX_ENA_R::new(((self.bits >> 27) & 1) != 0)
74    }
75    #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."]
76    #[inline(always)]
77    pub fn dma_tx_ena(&self) -> DMA_TX_ENA_R {
78        DMA_TX_ENA_R::new(((self.bits >> 28) & 1) != 0)
79    }
80}
81#[cfg(feature = "impl-register-debug")]
82impl core::fmt::Debug for R {
83    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
84        f.debug_struct("DMA_CONF")
85            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
86            .field("dma_infifo_full", &self.dma_infifo_full())
87            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
88            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
89            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
90            .field("rx_eof_en", &self.rx_eof_en())
91            .field("dma_rx_ena", &self.dma_rx_ena())
92            .field("dma_tx_ena", &self.dma_tx_ena())
93            .finish()
94    }
95}
96impl W {
97    #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
98    #[inline(always)]
99    pub fn dma_slv_seg_trans_en(&mut self) -> DMA_SLV_SEG_TRANS_EN_W<DMA_CONF_SPEC> {
100        DMA_SLV_SEG_TRANS_EN_W::new(self, 18)
101    }
102    #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
103    #[inline(always)]
104    pub fn slv_rx_seg_trans_clr_en(&mut self) -> SLV_RX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
105        SLV_RX_SEG_TRANS_CLR_EN_W::new(self, 19)
106    }
107    #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
108    #[inline(always)]
109    pub fn slv_tx_seg_trans_clr_en(&mut self) -> SLV_TX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
110        SLV_TX_SEG_TRANS_CLR_EN_W::new(self, 20)
111    }
112    #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
113    #[inline(always)]
114    pub fn rx_eof_en(&mut self) -> RX_EOF_EN_W<DMA_CONF_SPEC> {
115        RX_EOF_EN_W::new(self, 21)
116    }
117    #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."]
118    #[inline(always)]
119    pub fn dma_rx_ena(&mut self) -> DMA_RX_ENA_W<DMA_CONF_SPEC> {
120        DMA_RX_ENA_W::new(self, 27)
121    }
122    #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."]
123    #[inline(always)]
124    pub fn dma_tx_ena(&mut self) -> DMA_TX_ENA_W<DMA_CONF_SPEC> {
125        DMA_TX_ENA_W::new(self, 28)
126    }
127    #[doc = "Bit 29 - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."]
128    #[inline(always)]
129    pub fn rx_afifo_rst(&mut self) -> RX_AFIFO_RST_W<DMA_CONF_SPEC> {
130        RX_AFIFO_RST_W::new(self, 29)
131    }
132    #[doc = "Bit 30 - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."]
133    #[inline(always)]
134    pub fn buf_afifo_rst(&mut self) -> BUF_AFIFO_RST_W<DMA_CONF_SPEC> {
135        BUF_AFIFO_RST_W::new(self, 30)
136    }
137    #[doc = "Bit 31 - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."]
138    #[inline(always)]
139    pub fn dma_afifo_rst(&mut self) -> DMA_AFIFO_RST_W<DMA_CONF_SPEC> {
140        DMA_AFIFO_RST_W::new(self, 31)
141    }
142}
143#[doc = "SPI DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
144pub struct DMA_CONF_SPEC;
145impl crate::RegisterSpec for DMA_CONF_SPEC {
146    type Ux = u32;
147}
148#[doc = "`read()` method returns [`dma_conf::R`](R) reader structure"]
149impl crate::Readable for DMA_CONF_SPEC {}
150#[doc = "`write(|w| ..)` method takes [`dma_conf::W`](W) writer structure"]
151impl crate::Writable for DMA_CONF_SPEC {
152    type Safety = crate::Unsafe;
153    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
154    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
155}
156#[doc = "`reset()` method sets DMA_CONF to value 0x03"]
157impl crate::Resettable for DMA_CONF_SPEC {
158    const RESET_VALUE: u32 = 0x03;
159}