esp32c2/spi2/
clk_gate.rs

1#[doc = "Register `CLK_GATE` reader"]
2pub type R = crate::R<CLK_GATE_SPEC>;
3#[doc = "Register `CLK_GATE` writer"]
4pub type W = crate::W<CLK_GATE_SPEC>;
5#[doc = "Field `CLK_EN` reader - Set this bit to enable clk gate"]
6pub type CLK_EN_R = crate::BitReader;
7#[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"]
8pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MST_CLK_ACTIVE` reader - Set this bit to power on the SPI module clock."]
10pub type MST_CLK_ACTIVE_R = crate::BitReader;
11#[doc = "Field `MST_CLK_ACTIVE` writer - Set this bit to power on the SPI module clock."]
12pub type MST_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MST_CLK_SEL` reader - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."]
14pub type MST_CLK_SEL_R = crate::BitReader;
15#[doc = "Field `MST_CLK_SEL` writer - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."]
16pub type MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Set this bit to enable clk gate"]
19    #[inline(always)]
20    pub fn clk_en(&self) -> CLK_EN_R {
21        CLK_EN_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Set this bit to power on the SPI module clock."]
24    #[inline(always)]
25    pub fn mst_clk_active(&self) -> MST_CLK_ACTIVE_R {
26        MST_CLK_ACTIVE_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."]
29    #[inline(always)]
30    pub fn mst_clk_sel(&self) -> MST_CLK_SEL_R {
31        MST_CLK_SEL_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("CLK_GATE")
38            .field("clk_en", &self.clk_en())
39            .field("mst_clk_active", &self.mst_clk_active())
40            .field("mst_clk_sel", &self.mst_clk_sel())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Set this bit to enable clk gate"]
46    #[inline(always)]
47    pub fn clk_en(&mut self) -> CLK_EN_W<CLK_GATE_SPEC> {
48        CLK_EN_W::new(self, 0)
49    }
50    #[doc = "Bit 1 - Set this bit to power on the SPI module clock."]
51    #[inline(always)]
52    pub fn mst_clk_active(&mut self) -> MST_CLK_ACTIVE_W<CLK_GATE_SPEC> {
53        MST_CLK_ACTIVE_W::new(self, 1)
54    }
55    #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."]
56    #[inline(always)]
57    pub fn mst_clk_sel(&mut self) -> MST_CLK_SEL_W<CLK_GATE_SPEC> {
58        MST_CLK_SEL_W::new(self, 2)
59    }
60}
61#[doc = "SPI module clock and register clock control\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct CLK_GATE_SPEC;
63impl crate::RegisterSpec for CLK_GATE_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`clk_gate::R`](R) reader structure"]
67impl crate::Readable for CLK_GATE_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`clk_gate::W`](W) writer structure"]
69impl crate::Writable for CLK_GATE_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets CLK_GATE to value 0"]
75impl crate::Resettable for CLK_GATE_SPEC {
76    const RESET_VALUE: u32 = 0;
77}
esp32c2/spi2/clk_gate.rs

esp32c2/spi2/
clk_gate.rs
