esp32c2/spi1/
int_st.rs

1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `PER_END` reader - The status bit for SPI_MEM_PER_END_INT interrupt."]
4pub type PER_END_R = crate::BitReader;
5#[doc = "Field `PES_END` reader - The status bit for SPI_MEM_PES_END_INT interrupt."]
6pub type PES_END_R = crate::BitReader;
7#[doc = "Field `WPE_END` reader - The status bit for SPI_MEM_WPE_END_INT interrupt."]
8pub type WPE_END_R = crate::BitReader;
9#[doc = "Field `SLV_ST_END` reader - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."]
10pub type SLV_ST_END_R = crate::BitReader;
11#[doc = "Field `MST_ST_END` reader - The status bit for SPI_MEM_MST_ST_END_INT interrupt."]
12pub type MST_ST_END_R = crate::BitReader;
13#[doc = "Field `BROWN_OUT` reader - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."]
14pub type BROWN_OUT_R = crate::BitReader;
15impl R {
16    #[doc = "Bit 0 - The status bit for SPI_MEM_PER_END_INT interrupt."]
17    #[inline(always)]
18    pub fn per_end(&self) -> PER_END_R {
19        PER_END_R::new((self.bits & 1) != 0)
20    }
21    #[doc = "Bit 1 - The status bit for SPI_MEM_PES_END_INT interrupt."]
22    #[inline(always)]
23    pub fn pes_end(&self) -> PES_END_R {
24        PES_END_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    #[doc = "Bit 2 - The status bit for SPI_MEM_WPE_END_INT interrupt."]
27    #[inline(always)]
28    pub fn wpe_end(&self) -> WPE_END_R {
29        WPE_END_R::new(((self.bits >> 2) & 1) != 0)
30    }
31    #[doc = "Bit 3 - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."]
32    #[inline(always)]
33    pub fn slv_st_end(&self) -> SLV_ST_END_R {
34        SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
35    }
36    #[doc = "Bit 4 - The status bit for SPI_MEM_MST_ST_END_INT interrupt."]
37    #[inline(always)]
38    pub fn mst_st_end(&self) -> MST_ST_END_R {
39        MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
40    }
41    #[doc = "Bit 5 - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."]
42    #[inline(always)]
43    pub fn brown_out(&self) -> BROWN_OUT_R {
44        BROWN_OUT_R::new(((self.bits >> 5) & 1) != 0)
45    }
46}
47#[cfg(feature = "impl-register-debug")]
48impl core::fmt::Debug for R {
49    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
50        f.debug_struct("INT_ST")
51            .field("per_end", &self.per_end())
52            .field("pes_end", &self.pes_end())
53            .field("wpe_end", &self.wpe_end())
54            .field("slv_st_end", &self.slv_st_end())
55            .field("mst_st_end", &self.mst_st_end())
56            .field("brown_out", &self.brown_out())
57            .finish()
58    }
59}
60#[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct INT_ST_SPEC;
62impl crate::RegisterSpec for INT_ST_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
66impl crate::Readable for INT_ST_SPEC {}
67#[doc = "`reset()` method sets INT_ST to value 0"]
68impl crate::Resettable for INT_ST_SPEC {
69    const RESET_VALUE: u32 = 0;
70}
esp32c2/spi1/int_st.rs

esp32c2/spi1/
int_st.rs
