esp32c2/spi0/
misc.rs

1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `TRANS_END` reader - The bit is used to indicate the spi0_mst_st controlled transmitting is done."]
6pub type TRANS_END_R = crate::BitReader;
7#[doc = "Field `TRANS_END` writer - The bit is used to indicate the spi0_mst_st controlled transmitting is done."]
8pub type TRANS_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TRANS_END_INT_ENA` reader - The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done."]
10pub type TRANS_END_INT_ENA_R = crate::BitReader;
11#[doc = "Field `TRANS_END_INT_ENA` writer - The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done."]
12pub type TRANS_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CSPI_ST_TRANS_END` reader - The bit is used to indicate the spi0_slv_st controlled transmitting is done."]
14pub type CSPI_ST_TRANS_END_R = crate::BitReader;
15#[doc = "Field `CSPI_ST_TRANS_END` writer - The bit is used to indicate the spi0_slv_st controlled transmitting is done."]
16pub type CSPI_ST_TRANS_END_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CSPI_ST_TRANS_END_INT_ENA` reader - The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done."]
18pub type CSPI_ST_TRANS_END_INT_ENA_R = crate::BitReader;
19#[doc = "Field `CSPI_ST_TRANS_END_INT_ENA` writer - The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done."]
20pub type CSPI_ST_TRANS_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
22pub type CK_IDLE_EDGE_R = crate::BitReader;
23#[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
24pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set."]
26pub type CS_KEEP_ACTIVE_R = crate::BitReader;
27#[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set."]
28pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 3 - The bit is used to indicate the spi0_mst_st controlled transmitting is done."]
31    #[inline(always)]
32    pub fn trans_end(&self) -> TRANS_END_R {
33        TRANS_END_R::new(((self.bits >> 3) & 1) != 0)
34    }
35    #[doc = "Bit 4 - The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done."]
36    #[inline(always)]
37    pub fn trans_end_int_ena(&self) -> TRANS_END_INT_ENA_R {
38        TRANS_END_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
39    }
40    #[doc = "Bit 5 - The bit is used to indicate the spi0_slv_st controlled transmitting is done."]
41    #[inline(always)]
42    pub fn cspi_st_trans_end(&self) -> CSPI_ST_TRANS_END_R {
43        CSPI_ST_TRANS_END_R::new(((self.bits >> 5) & 1) != 0)
44    }
45    #[doc = "Bit 6 - The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done."]
46    #[inline(always)]
47    pub fn cspi_st_trans_end_int_ena(&self) -> CSPI_ST_TRANS_END_INT_ENA_R {
48        CSPI_ST_TRANS_END_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
49    }
50    #[doc = "Bit 9 - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
51    #[inline(always)]
52    pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
53        CK_IDLE_EDGE_R::new(((self.bits >> 9) & 1) != 0)
54    }
55    #[doc = "Bit 10 - spi cs line keep low when the bit is set."]
56    #[inline(always)]
57    pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
58        CS_KEEP_ACTIVE_R::new(((self.bits >> 10) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("MISC")
65            .field("trans_end", &self.trans_end())
66            .field("trans_end_int_ena", &self.trans_end_int_ena())
67            .field("cspi_st_trans_end", &self.cspi_st_trans_end())
68            .field(
69                "cspi_st_trans_end_int_ena",
70                &self.cspi_st_trans_end_int_ena(),
71            )
72            .field("ck_idle_edge", &self.ck_idle_edge())
73            .field("cs_keep_active", &self.cs_keep_active())
74            .finish()
75    }
76}
77impl W {
78    #[doc = "Bit 3 - The bit is used to indicate the spi0_mst_st controlled transmitting is done."]
79    #[inline(always)]
80    pub fn trans_end(&mut self) -> TRANS_END_W<MISC_SPEC> {
81        TRANS_END_W::new(self, 3)
82    }
83    #[doc = "Bit 4 - The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done."]
84    #[inline(always)]
85    pub fn trans_end_int_ena(&mut self) -> TRANS_END_INT_ENA_W<MISC_SPEC> {
86        TRANS_END_INT_ENA_W::new(self, 4)
87    }
88    #[doc = "Bit 5 - The bit is used to indicate the spi0_slv_st controlled transmitting is done."]
89    #[inline(always)]
90    pub fn cspi_st_trans_end(&mut self) -> CSPI_ST_TRANS_END_W<MISC_SPEC> {
91        CSPI_ST_TRANS_END_W::new(self, 5)
92    }
93    #[doc = "Bit 6 - The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done."]
94    #[inline(always)]
95    pub fn cspi_st_trans_end_int_ena(&mut self) -> CSPI_ST_TRANS_END_INT_ENA_W<MISC_SPEC> {
96        CSPI_ST_TRANS_END_INT_ENA_W::new(self, 6)
97    }
98    #[doc = "Bit 9 - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
99    #[inline(always)]
100    pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
101        CK_IDLE_EDGE_W::new(self, 9)
102    }
103    #[doc = "Bit 10 - spi cs line keep low when the bit is set."]
104    #[inline(always)]
105    pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
106        CS_KEEP_ACTIVE_W::new(self, 10)
107    }
108}
109#[doc = "SPI0 misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
110pub struct MISC_SPEC;
111impl crate::RegisterSpec for MISC_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
115impl crate::Readable for MISC_SPEC {}
116#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
117impl crate::Writable for MISC_SPEC {
118    type Safety = crate::Unsafe;
119    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
120    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
121}
122#[doc = "`reset()` method sets MISC to value 0"]
123impl crate::Resettable for MISC_SPEC {
124    const RESET_VALUE: u32 = 0;
125}
esp32c2/spi0/misc.rs

esp32c2/spi0/
misc.rs
