esp32c2/spi0/
ctrl1.rs

1#[doc = "Register `CTRL1` reader"]
2pub type R = crate::R<CTRL1_SPEC>;
3#[doc = "Register `CTRL1` writer"]
4pub type W = crate::W<CTRL1_SPEC>;
5#[doc = "Field `CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
6pub type CLK_MODE_R = crate::FieldReader;
7#[doc = "Field `CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
8pub type CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `RXFIFO_RST` writer - SPI0 RX FIFO reset signal."]
10pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
11impl R {
12    #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
13    #[inline(always)]
14    pub fn clk_mode(&self) -> CLK_MODE_R {
15        CLK_MODE_R::new((self.bits & 3) as u8)
16    }
17}
18#[cfg(feature = "impl-register-debug")]
19impl core::fmt::Debug for R {
20    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21        f.debug_struct("CTRL1")
22            .field("clk_mode", &self.clk_mode())
23            .finish()
24    }
25}
26impl W {
27    #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
28    #[inline(always)]
29    pub fn clk_mode(&mut self) -> CLK_MODE_W<CTRL1_SPEC> {
30        CLK_MODE_W::new(self, 0)
31    }
32    #[doc = "Bit 30 - SPI0 RX FIFO reset signal."]
33    #[inline(always)]
34    pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CTRL1_SPEC> {
35        RXFIFO_RST_W::new(self, 30)
36    }
37}
38#[doc = "SPI0 control1 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
39pub struct CTRL1_SPEC;
40impl crate::RegisterSpec for CTRL1_SPEC {
41    type Ux = u32;
42}
43#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
44impl crate::Readable for CTRL1_SPEC {}
45#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
46impl crate::Writable for CTRL1_SPEC {
47    type Safety = crate::Unsafe;
48    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
49    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
50}
51#[doc = "`reset()` method sets CTRL1 to value 0"]
52impl crate::Resettable for CTRL1_SPEC {
53    const RESET_VALUE: u32 = 0;
54}
esp32c2/spi0/ctrl1.rs

esp32c2/spi0/
ctrl1.rs
