1#[doc = "Register `CACHE_FCTRL` reader"]
2pub type R = crate::R<CACHE_FCTRL_SPEC>;
3#[doc = "Register `CACHE_FCTRL` writer"]
4pub type W = crate::W<CACHE_FCTRL_SPEC>;
5#[doc = "Field `CACHE_REQ_EN` reader - For SPI0, Cache access enable, 1: enable, 0:disable."]
6pub type CACHE_REQ_EN_R = crate::BitReader;
7#[doc = "Field `CACHE_REQ_EN` writer - For SPI0, Cache access enable, 1: enable, 0:disable."]
8pub type CACHE_REQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CACHE_USR_ADDR_4BYTE` reader - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
10pub type CACHE_USR_ADDR_4BYTE_R = crate::BitReader;
11#[doc = "Field `CACHE_USR_ADDR_4BYTE` writer - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
12pub type CACHE_USR_ADDR_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CACHE_FLASH_USR_CMD` reader - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
14pub type CACHE_FLASH_USR_CMD_R = crate::BitReader;
15#[doc = "Field `CACHE_FLASH_USR_CMD` writer - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
16pub type CACHE_FLASH_USR_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FDIN_DUAL` reader - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
18pub type FDIN_DUAL_R = crate::BitReader;
19#[doc = "Field `FDIN_DUAL` writer - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
20pub type FDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FDOUT_DUAL` reader - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
22pub type FDOUT_DUAL_R = crate::BitReader;
23#[doc = "Field `FDOUT_DUAL` writer - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
24pub type FDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FADDR_DUAL` reader - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
26pub type FADDR_DUAL_R = crate::BitReader;
27#[doc = "Field `FADDR_DUAL` writer - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
28pub type FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FDIN_QUAD` reader - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
30pub type FDIN_QUAD_R = crate::BitReader;
31#[doc = "Field `FDIN_QUAD` writer - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
32pub type FDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FDOUT_QUAD` reader - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
34pub type FDOUT_QUAD_R = crate::BitReader;
35#[doc = "Field `FDOUT_QUAD` writer - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
36pub type FDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FADDR_QUAD` reader - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
38pub type FADDR_QUAD_R = crate::BitReader;
39#[doc = "Field `FADDR_QUAD` writer - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
40pub type FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - For SPI0, Cache access enable, 1: enable, 0:disable."]
43 #[inline(always)]
44 pub fn cache_req_en(&self) -> CACHE_REQ_EN_R {
45 CACHE_REQ_EN_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
48 #[inline(always)]
49 pub fn cache_usr_addr_4byte(&self) -> CACHE_USR_ADDR_4BYTE_R {
50 CACHE_USR_ADDR_4BYTE_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
53 #[inline(always)]
54 pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R {
55 CACHE_FLASH_USR_CMD_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
58 #[inline(always)]
59 pub fn fdin_dual(&self) -> FDIN_DUAL_R {
60 FDIN_DUAL_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
63 #[inline(always)]
64 pub fn fdout_dual(&self) -> FDOUT_DUAL_R {
65 FDOUT_DUAL_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
68 #[inline(always)]
69 pub fn faddr_dual(&self) -> FADDR_DUAL_R {
70 FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0)
71 }
72 #[doc = "Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
73 #[inline(always)]
74 pub fn fdin_quad(&self) -> FDIN_QUAD_R {
75 FDIN_QUAD_R::new(((self.bits >> 6) & 1) != 0)
76 }
77 #[doc = "Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
78 #[inline(always)]
79 pub fn fdout_quad(&self) -> FDOUT_QUAD_R {
80 FDOUT_QUAD_R::new(((self.bits >> 7) & 1) != 0)
81 }
82 #[doc = "Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
83 #[inline(always)]
84 pub fn faddr_quad(&self) -> FADDR_QUAD_R {
85 FADDR_QUAD_R::new(((self.bits >> 8) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("CACHE_FCTRL")
92 .field("cache_req_en", &self.cache_req_en())
93 .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
94 .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
95 .field("fdin_dual", &self.fdin_dual())
96 .field("fdout_dual", &self.fdout_dual())
97 .field("faddr_dual", &self.faddr_dual())
98 .field("fdin_quad", &self.fdin_quad())
99 .field("fdout_quad", &self.fdout_quad())
100 .field("faddr_quad", &self.faddr_quad())
101 .finish()
102 }
103}
104impl W {
105 #[doc = "Bit 0 - For SPI0, Cache access enable, 1: enable, 0:disable."]
106 #[inline(always)]
107 pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<CACHE_FCTRL_SPEC> {
108 CACHE_REQ_EN_W::new(self, 0)
109 }
110 #[doc = "Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
111 #[inline(always)]
112 pub fn cache_usr_addr_4byte(&mut self) -> CACHE_USR_ADDR_4BYTE_W<CACHE_FCTRL_SPEC> {
113 CACHE_USR_ADDR_4BYTE_W::new(self, 1)
114 }
115 #[doc = "Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
116 #[inline(always)]
117 pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<CACHE_FCTRL_SPEC> {
118 CACHE_FLASH_USR_CMD_W::new(self, 2)
119 }
120 #[doc = "Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
121 #[inline(always)]
122 pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<CACHE_FCTRL_SPEC> {
123 FDIN_DUAL_W::new(self, 3)
124 }
125 #[doc = "Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
126 #[inline(always)]
127 pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<CACHE_FCTRL_SPEC> {
128 FDOUT_DUAL_W::new(self, 4)
129 }
130 #[doc = "Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
131 #[inline(always)]
132 pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CACHE_FCTRL_SPEC> {
133 FADDR_DUAL_W::new(self, 5)
134 }
135 #[doc = "Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
136 #[inline(always)]
137 pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<CACHE_FCTRL_SPEC> {
138 FDIN_QUAD_W::new(self, 6)
139 }
140 #[doc = "Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
141 #[inline(always)]
142 pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<CACHE_FCTRL_SPEC> {
143 FDOUT_QUAD_W::new(self, 7)
144 }
145 #[doc = "Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
146 #[inline(always)]
147 pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CACHE_FCTRL_SPEC> {
148 FADDR_QUAD_W::new(self, 8)
149 }
150}
151#[doc = "SPI0 bit mode control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_fctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_fctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct CACHE_FCTRL_SPEC;
153impl crate::RegisterSpec for CACHE_FCTRL_SPEC {
154 type Ux = u32;
155}
156#[doc = "`read()` method returns [`cache_fctrl::R`](R) reader structure"]
157impl crate::Readable for CACHE_FCTRL_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`cache_fctrl::W`](W) writer structure"]
159impl crate::Writable for CACHE_FCTRL_SPEC {
160 type Safety = crate::Unsafe;
161 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets CACHE_FCTRL to value 0"]
165impl crate::Resettable for CACHE_FCTRL_SPEC {
166 const RESET_VALUE: u32 = 0;
167}