esp32c2/
spi0.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    _reserved0: [u8; 0x08],
6    ctrl: CTRL,
7    ctrl1: CTRL1,
8    ctrl2: CTRL2,
9    clock: CLOCK,
10    user: USER,
11    user1: USER1,
12    user2: USER2,
13    _reserved7: [u8; 0x08],
14    rd_status: RD_STATUS,
15    _reserved8: [u8; 0x04],
16    misc: MISC,
17    _reserved9: [u8; 0x04],
18    cache_fctrl: CACHE_FCTRL,
19    _reserved10: [u8; 0x14],
20    fsm: FSM,
21    _reserved11: [u8; 0x50],
22    timing_cali: TIMING_CALI,
23    din_mode: DIN_MODE,
24    din_num: DIN_NUM,
25    dout_mode: DOUT_MODE,
26    _reserved15: [u8; 0x24],
27    clock_gate: CLOCK_GATE,
28    core_clk_sel: CORE_CLK_SEL,
29    _reserved17: [u8; 0x0318],
30    date: DATE,
31}
32impl RegisterBlock {
33    #[doc = "0x08 - SPI0 control register."]
34    #[inline(always)]
35    pub const fn ctrl(&self) -> &CTRL {
36        &self.ctrl
37    }
38    #[doc = "0x0c - SPI0 control1 register."]
39    #[inline(always)]
40    pub const fn ctrl1(&self) -> &CTRL1 {
41        &self.ctrl1
42    }
43    #[doc = "0x10 - SPI0 control2 register."]
44    #[inline(always)]
45    pub const fn ctrl2(&self) -> &CTRL2 {
46        &self.ctrl2
47    }
48    #[doc = "0x14 - SPI clock division control register."]
49    #[inline(always)]
50    pub const fn clock(&self) -> &CLOCK {
51        &self.clock
52    }
53    #[doc = "0x18 - SPI0 user register."]
54    #[inline(always)]
55    pub const fn user(&self) -> &USER {
56        &self.user
57    }
58    #[doc = "0x1c - SPI0 user1 register."]
59    #[inline(always)]
60    pub const fn user1(&self) -> &USER1 {
61        &self.user1
62    }
63    #[doc = "0x20 - SPI0 user2 register."]
64    #[inline(always)]
65    pub const fn user2(&self) -> &USER2 {
66        &self.user2
67    }
68    #[doc = "0x2c - SPI0 read control register."]
69    #[inline(always)]
70    pub const fn rd_status(&self) -> &RD_STATUS {
71        &self.rd_status
72    }
73    #[doc = "0x34 - SPI0 misc register"]
74    #[inline(always)]
75    pub const fn misc(&self) -> &MISC {
76        &self.misc
77    }
78    #[doc = "0x3c - SPI0 bit mode control register."]
79    #[inline(always)]
80    pub const fn cache_fctrl(&self) -> &CACHE_FCTRL {
81        &self.cache_fctrl
82    }
83    #[doc = "0x54 - SPI0 FSM status register"]
84    #[inline(always)]
85    pub const fn fsm(&self) -> &FSM {
86        &self.fsm
87    }
88    #[doc = "0xa8 - SPI0 timing calibration register"]
89    #[inline(always)]
90    pub const fn timing_cali(&self) -> &TIMING_CALI {
91        &self.timing_cali
92    }
93    #[doc = "0xac - SPI0 input delay mode control register"]
94    #[inline(always)]
95    pub const fn din_mode(&self) -> &DIN_MODE {
96        &self.din_mode
97    }
98    #[doc = "0xb0 - SPI0 input delay number control register"]
99    #[inline(always)]
100    pub const fn din_num(&self) -> &DIN_NUM {
101        &self.din_num
102    }
103    #[doc = "0xb4 - SPI0 output delay mode control register"]
104    #[inline(always)]
105    pub const fn dout_mode(&self) -> &DOUT_MODE {
106        &self.dout_mode
107    }
108    #[doc = "0xdc - SPI0 clk_gate register"]
109    #[inline(always)]
110    pub const fn clock_gate(&self) -> &CLOCK_GATE {
111        &self.clock_gate
112    }
113    #[doc = "0xe0 - SPI0 module clock select register"]
114    #[inline(always)]
115    pub const fn core_clk_sel(&self) -> &CORE_CLK_SEL {
116        &self.core_clk_sel
117    }
118    #[doc = "0x3fc - Version control register"]
119    #[inline(always)]
120    pub const fn date(&self) -> &DATE {
121        &self.date
122    }
123}
124#[doc = "CTRL (rw) register accessor: SPI0 control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
125pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
126#[doc = "SPI0 control register."]
127pub mod ctrl;
128#[doc = "CTRL1 (rw) register accessor: SPI0 control1 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"]
129pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
130#[doc = "SPI0 control1 register."]
131pub mod ctrl1;
132#[doc = "CTRL2 (rw) register accessor: SPI0 control2 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"]
133pub type CTRL2 = crate::Reg<ctrl2::CTRL2_SPEC>;
134#[doc = "SPI0 control2 register."]
135pub mod ctrl2;
136#[doc = "CLOCK (rw) register accessor: SPI clock division control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock`] module"]
137pub type CLOCK = crate::Reg<clock::CLOCK_SPEC>;
138#[doc = "SPI clock division control register."]
139pub mod clock;
140#[doc = "USER (rw) register accessor: SPI0 user register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user`] module"]
141pub type USER = crate::Reg<user::USER_SPEC>;
142#[doc = "SPI0 user register."]
143pub mod user;
144#[doc = "USER1 (rw) register accessor: SPI0 user1 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user1`] module"]
145pub type USER1 = crate::Reg<user1::USER1_SPEC>;
146#[doc = "SPI0 user1 register."]
147pub mod user1;
148#[doc = "USER2 (rw) register accessor: SPI0 user2 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user2`] module"]
149pub type USER2 = crate::Reg<user2::USER2_SPEC>;
150#[doc = "SPI0 user2 register."]
151pub mod user2;
152#[doc = "RD_STATUS (rw) register accessor: SPI0 read control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`rd_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rd_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_status`] module"]
153pub type RD_STATUS = crate::Reg<rd_status::RD_STATUS_SPEC>;
154#[doc = "SPI0 read control register."]
155pub mod rd_status;
156#[doc = "MISC (rw) register accessor: SPI0 misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc`] module"]
157pub type MISC = crate::Reg<misc::MISC_SPEC>;
158#[doc = "SPI0 misc register"]
159pub mod misc;
160#[doc = "CACHE_FCTRL (rw) register accessor: SPI0 bit mode control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_fctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_fctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_fctrl`] module"]
161pub type CACHE_FCTRL = crate::Reg<cache_fctrl::CACHE_FCTRL_SPEC>;
162#[doc = "SPI0 bit mode control register."]
163pub mod cache_fctrl;
164#[doc = "FSM (rw) register accessor: SPI0 FSM status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm`] module"]
165pub type FSM = crate::Reg<fsm::FSM_SPEC>;
166#[doc = "SPI0 FSM status register"]
167pub mod fsm;
168#[doc = "TIMING_CALI (r) register accessor: SPI0 timing calibration register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing_cali::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing_cali`] module"]
169pub type TIMING_CALI = crate::Reg<timing_cali::TIMING_CALI_SPEC>;
170#[doc = "SPI0 timing calibration register"]
171pub mod timing_cali;
172#[doc = "DIN_MODE (r) register accessor: SPI0 input delay mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`din_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din_mode`] module"]
173pub type DIN_MODE = crate::Reg<din_mode::DIN_MODE_SPEC>;
174#[doc = "SPI0 input delay mode control register"]
175pub mod din_mode;
176#[doc = "DIN_NUM (r) register accessor: SPI0 input delay number control register\n\nYou can [`read`](crate::Reg::read) this register and get [`din_num::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din_num`] module"]
177pub type DIN_NUM = crate::Reg<din_num::DIN_NUM_SPEC>;
178#[doc = "SPI0 input delay number control register"]
179pub mod din_num;
180#[doc = "DOUT_MODE (r) register accessor: SPI0 output delay mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dout_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout_mode`] module"]
181pub type DOUT_MODE = crate::Reg<dout_mode::DOUT_MODE_SPEC>;
182#[doc = "SPI0 output delay mode control register"]
183pub mod dout_mode;
184#[doc = "CLOCK_GATE (rw) register accessor: SPI0 clk_gate register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
185pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
186#[doc = "SPI0 clk_gate register"]
187pub mod clock_gate;
188#[doc = "CORE_CLK_SEL (rw) register accessor: SPI0 module clock select register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_clk_sel`] module"]
189pub type CORE_CLK_SEL = crate::Reg<core_clk_sel::CORE_CLK_SEL_SPEC>;
190#[doc = "SPI0 module clock select register"]
191pub mod core_clk_sel;
192#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
193pub type DATE = crate::Reg<date::DATE_SPEC>;
194#[doc = "Version control register"]
195pub mod date;