esp32c2/sha/
h_mem.rs

1#[doc = "Register `H_MEM[%s]` reader"]
2pub type R = crate::R<H_MEM_SPEC>;
3#[doc = "Register `H_MEM[%s]` writer"]
4pub type W = crate::W<H_MEM_SPEC>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for R {
7    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8        write!(f, "{}", self.bits())
9    }
10}
11impl W {}
12#[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13pub struct H_MEM_SPEC;
14impl crate::RegisterSpec for H_MEM_SPEC {
15    type Ux = u32;
16}
17#[doc = "`read()` method returns [`h_mem::R`](R) reader structure"]
18impl crate::Readable for H_MEM_SPEC {}
19#[doc = "`write(|w| ..)` method takes [`h_mem::W`](W) writer structure"]
20impl crate::Writable for H_MEM_SPEC {
21    type Safety = crate::Unsafe;
22    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
23    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
24}
25#[doc = "`reset()` method sets H_MEM[%s] to value 0"]
26impl crate::Resettable for H_MEM_SPEC {
27    const RESET_VALUE: u32 = 0;
28}
esp32c2/sha/h_mem.rs

esp32c2/sha/
h_mem.rs
