1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 mode: MODE,
6 t_string: T_STRING,
7 t_length: T_LENGTH,
8 dma_block_num: DMA_BLOCK_NUM,
9 start: START,
10 continue_: CONTINUE,
11 busy: BUSY,
12 dma_start: DMA_START,
13 dma_continue: DMA_CONTINUE,
14 clear_irq: CLEAR_IRQ,
15 irq_ena: IRQ_ENA,
16 date: DATE,
17 _reserved12: [u8; 0x10],
18 h_mem: [H_MEM; 8],
19 _reserved13: [u8; 0x20],
20 m_mem: [M_MEM; 16],
21}
22impl RegisterBlock {
23 #[doc = "0x00 - Initial configuration register."]
24 #[inline(always)]
25 pub const fn mode(&self) -> &MODE {
26 &self.mode
27 }
28 #[doc = "0x04 - SHA 512/t configuration register 0."]
29 #[inline(always)]
30 pub const fn t_string(&self) -> &T_STRING {
31 &self.t_string
32 }
33 #[doc = "0x08 - SHA 512/t configuration register 1."]
34 #[inline(always)]
35 pub const fn t_length(&self) -> &T_LENGTH {
36 &self.t_length
37 }
38 #[doc = "0x0c - DMA configuration register 0."]
39 #[inline(always)]
40 pub const fn dma_block_num(&self) -> &DMA_BLOCK_NUM {
41 &self.dma_block_num
42 }
43 #[doc = "0x10 - Typical SHA configuration register 0."]
44 #[inline(always)]
45 pub const fn start(&self) -> &START {
46 &self.start
47 }
48 #[doc = "0x14 - Typical SHA configuration register 1."]
49 #[inline(always)]
50 pub const fn continue_(&self) -> &CONTINUE {
51 &self.continue_
52 }
53 #[doc = "0x18 - Busy register."]
54 #[inline(always)]
55 pub const fn busy(&self) -> &BUSY {
56 &self.busy
57 }
58 #[doc = "0x1c - DMA configuration register 1."]
59 #[inline(always)]
60 pub const fn dma_start(&self) -> &DMA_START {
61 &self.dma_start
62 }
63 #[doc = "0x20 - DMA configuration register 2."]
64 #[inline(always)]
65 pub const fn dma_continue(&self) -> &DMA_CONTINUE {
66 &self.dma_continue
67 }
68 #[doc = "0x24 - Interrupt clear register."]
69 #[inline(always)]
70 pub const fn clear_irq(&self) -> &CLEAR_IRQ {
71 &self.clear_irq
72 }
73 #[doc = "0x28 - Interrupt enable register."]
74 #[inline(always)]
75 pub const fn irq_ena(&self) -> &IRQ_ENA {
76 &self.irq_ena
77 }
78 #[doc = "0x2c - Date register."]
79 #[inline(always)]
80 pub const fn date(&self) -> &DATE {
81 &self.date
82 }
83 #[doc = "0x40..0x60 - Sha H memory which contains intermediate hash or finial hash."]
84 #[inline(always)]
85 pub const fn h_mem(&self, n: usize) -> &H_MEM {
86 &self.h_mem[n]
87 }
88 #[doc = "Iterator for array of:"]
89 #[doc = "0x40..0x60 - Sha H memory which contains intermediate hash or finial hash."]
90 #[inline(always)]
91 pub fn h_mem_iter(&self) -> impl Iterator<Item = &H_MEM> {
92 self.h_mem.iter()
93 }
94 #[doc = "0x80..0xc0 - Sha M memory which contains message."]
95 #[inline(always)]
96 pub const fn m_mem(&self, n: usize) -> &M_MEM {
97 &self.m_mem[n]
98 }
99 #[doc = "Iterator for array of:"]
100 #[doc = "0x80..0xc0 - Sha M memory which contains message."]
101 #[inline(always)]
102 pub fn m_mem_iter(&self) -> impl Iterator<Item = &M_MEM> {
103 self.m_mem.iter()
104 }
105}
106#[doc = "MODE (rw) register accessor: Initial configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"]
107pub type MODE = crate::Reg<mode::MODE_SPEC>;
108#[doc = "Initial configuration register."]
109pub mod mode;
110#[doc = "T_STRING (rw) register accessor: SHA 512/t configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`t_string::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t_string::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t_string`] module"]
111pub type T_STRING = crate::Reg<t_string::T_STRING_SPEC>;
112#[doc = "SHA 512/t configuration register 0."]
113pub mod t_string;
114#[doc = "T_LENGTH (rw) register accessor: SHA 512/t configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`t_length::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t_length::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t_length`] module"]
115pub type T_LENGTH = crate::Reg<t_length::T_LENGTH_SPEC>;
116#[doc = "SHA 512/t configuration register 1."]
117pub mod t_length;
118#[doc = "DMA_BLOCK_NUM (rw) register accessor: DMA configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_block_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_block_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_block_num`] module"]
119pub type DMA_BLOCK_NUM = crate::Reg<dma_block_num::DMA_BLOCK_NUM_SPEC>;
120#[doc = "DMA configuration register 0."]
121pub mod dma_block_num;
122#[doc = "START (w) register accessor: Typical SHA configuration register 0.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@start`] module"]
123pub type START = crate::Reg<start::START_SPEC>;
124#[doc = "Typical SHA configuration register 0."]
125pub mod start;
126#[doc = "CONTINUE (w) register accessor: Typical SHA configuration register 1.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`continue_::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@continue_`] module"]
127pub type CONTINUE = crate::Reg<continue_::CONTINUE_SPEC>;
128#[doc = "Typical SHA configuration register 1."]
129pub mod continue_;
130#[doc = "BUSY (r) register accessor: Busy register.\n\nYou can [`read`](crate::Reg::read) this register and get [`busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busy`] module"]
131pub type BUSY = crate::Reg<busy::BUSY_SPEC>;
132#[doc = "Busy register."]
133pub mod busy;
134#[doc = "DMA_START (w) register accessor: DMA configuration register 1.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_start`] module"]
135pub type DMA_START = crate::Reg<dma_start::DMA_START_SPEC>;
136#[doc = "DMA configuration register 1."]
137pub mod dma_start;
138#[doc = "DMA_CONTINUE (w) register accessor: DMA configuration register 2.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_continue::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_continue`] module"]
139pub type DMA_CONTINUE = crate::Reg<dma_continue::DMA_CONTINUE_SPEC>;
140#[doc = "DMA configuration register 2."]
141pub mod dma_continue;
142#[doc = "CLEAR_IRQ (w) register accessor: Interrupt clear register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clear_irq::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear_irq`] module"]
143pub type CLEAR_IRQ = crate::Reg<clear_irq::CLEAR_IRQ_SPEC>;
144#[doc = "Interrupt clear register."]
145pub mod clear_irq;
146#[doc = "IRQ_ENA (rw) register accessor: Interrupt enable register.\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_ena`] module"]
147pub type IRQ_ENA = crate::Reg<irq_ena::IRQ_ENA_SPEC>;
148#[doc = "Interrupt enable register."]
149pub mod irq_ena;
150#[doc = "DATE (rw) register accessor: Date register.\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
151pub type DATE = crate::Reg<date::DATE_SPEC>;
152#[doc = "Date register."]
153pub mod date;
154#[doc = "H_MEM (rw) register accessor: Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h_mem`] module"]
155pub type H_MEM = crate::Reg<h_mem::H_MEM_SPEC>;
156#[doc = "Sha H memory which contains intermediate hash or finial hash."]
157pub mod h_mem;
158#[doc = "M_MEM (rw) register accessor: Sha M memory which contains message.\n\nYou can [`read`](crate::Reg::read) this register and get [`m_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@m_mem`] module"]
159pub type M_MEM = crate::Reg<m_mem::M_MEM_SPEC>;
160#[doc = "Sha M memory which contains message."]
161pub mod m_mem;