esp32c2/sensitive/
cache_tag_access_1.rs

1#[doc = "Register `CACHE_TAG_ACCESS_1` reader"]
2pub type R = crate::R<CACHE_TAG_ACCESS_1_SPEC>;
3#[doc = "Register `CACHE_TAG_ACCESS_1` writer"]
4pub type W = crate::W<CACHE_TAG_ACCESS_1_SPEC>;
5#[doc = "Field `PRO_I_TAG_RD_ACS` reader - Need add description"]
6pub type PRO_I_TAG_RD_ACS_R = crate::BitReader;
7#[doc = "Field `PRO_I_TAG_RD_ACS` writer - Need add description"]
8pub type PRO_I_TAG_RD_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_I_TAG_WR_ACS` reader - Need add description"]
10pub type PRO_I_TAG_WR_ACS_R = crate::BitReader;
11#[doc = "Field `PRO_I_TAG_WR_ACS` writer - Need add description"]
12pub type PRO_I_TAG_WR_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_D_TAG_RD_ACS` reader - Need add description"]
14pub type PRO_D_TAG_RD_ACS_R = crate::BitReader;
15#[doc = "Field `PRO_D_TAG_RD_ACS` writer - Need add description"]
16pub type PRO_D_TAG_RD_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PRO_D_TAG_WR_ACS` reader - Need add description"]
18pub type PRO_D_TAG_WR_ACS_R = crate::BitReader;
19#[doc = "Field `PRO_D_TAG_WR_ACS` writer - Need add description"]
20pub type PRO_D_TAG_WR_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Need add description"]
23    #[inline(always)]
24    pub fn pro_i_tag_rd_acs(&self) -> PRO_I_TAG_RD_ACS_R {
25        PRO_I_TAG_RD_ACS_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Need add description"]
28    #[inline(always)]
29    pub fn pro_i_tag_wr_acs(&self) -> PRO_I_TAG_WR_ACS_R {
30        PRO_I_TAG_WR_ACS_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Need add description"]
33    #[inline(always)]
34    pub fn pro_d_tag_rd_acs(&self) -> PRO_D_TAG_RD_ACS_R {
35        PRO_D_TAG_RD_ACS_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - Need add description"]
38    #[inline(always)]
39    pub fn pro_d_tag_wr_acs(&self) -> PRO_D_TAG_WR_ACS_R {
40        PRO_D_TAG_WR_ACS_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CACHE_TAG_ACCESS_1")
47            .field("pro_i_tag_rd_acs", &self.pro_i_tag_rd_acs())
48            .field("pro_i_tag_wr_acs", &self.pro_i_tag_wr_acs())
49            .field("pro_d_tag_rd_acs", &self.pro_d_tag_rd_acs())
50            .field("pro_d_tag_wr_acs", &self.pro_d_tag_wr_acs())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0 - Need add description"]
56    #[inline(always)]
57    pub fn pro_i_tag_rd_acs(&mut self) -> PRO_I_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
58        PRO_I_TAG_RD_ACS_W::new(self, 0)
59    }
60    #[doc = "Bit 1 - Need add description"]
61    #[inline(always)]
62    pub fn pro_i_tag_wr_acs(&mut self) -> PRO_I_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
63        PRO_I_TAG_WR_ACS_W::new(self, 1)
64    }
65    #[doc = "Bit 2 - Need add description"]
66    #[inline(always)]
67    pub fn pro_d_tag_rd_acs(&mut self) -> PRO_D_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
68        PRO_D_TAG_RD_ACS_W::new(self, 2)
69    }
70    #[doc = "Bit 3 - Need add description"]
71    #[inline(always)]
72    pub fn pro_d_tag_wr_acs(&mut self) -> PRO_D_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
73        PRO_D_TAG_WR_ACS_W::new(self, 3)
74    }
75}
76#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_access_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_access_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CACHE_TAG_ACCESS_1_SPEC;
78impl crate::RegisterSpec for CACHE_TAG_ACCESS_1_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`cache_tag_access_1::R`](R) reader structure"]
82impl crate::Readable for CACHE_TAG_ACCESS_1_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`cache_tag_access_1::W`](W) writer structure"]
84impl crate::Writable for CACHE_TAG_ACCESS_1_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets CACHE_TAG_ACCESS_1 to value 0x0f"]
90impl crate::Resettable for CACHE_TAG_ACCESS_1_SPEC {
91    const RESET_VALUE: u32 = 0x0f;
92}
esp32c2/sensitive/cache_tag_access_1.rs

esp32c2/sensitive/
cache_tag_access_1.rs
