esp32c2/rtc_cntl/
int_clr.rs

1#[doc = "Register `INT_CLR` reader"]
2pub type R = crate::R<INT_CLR_SPEC>;
3#[doc = "Register `INT_CLR` writer"]
4pub type W = crate::W<INT_CLR_SPEC>;
5#[doc = "Field `SLP_WAKEUP` reader - Clear sleep wakeup interrupt state"]
6pub type SLP_WAKEUP_R = crate::BitReader;
7#[doc = "Field `SLP_WAKEUP` writer - Clear sleep wakeup interrupt state"]
8pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SLP_REJECT` reader - Clear sleep reject interrupt state"]
10pub type SLP_REJECT_R = crate::BitReader;
11#[doc = "Field `SLP_REJECT` writer - Clear sleep reject interrupt state"]
12pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `WDT` reader - Clear RTC WDT interrupt state"]
14pub type WDT_R = crate::BitReader;
15#[doc = "Field `WDT` writer - Clear RTC WDT interrupt state"]
16pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `BROWN_OUT` reader - Clear brown out interrupt state"]
18pub type BROWN_OUT_R = crate::BitReader;
19#[doc = "Field `BROWN_OUT` writer - Clear brown out interrupt state"]
20pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `MAIN_TIMER` reader - Clear RTC main timer interrupt state"]
22pub type MAIN_TIMER_R = crate::BitReader;
23#[doc = "Field `MAIN_TIMER` writer - Clear RTC main timer interrupt state"]
24pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `SWD` reader - Clear super watch dog interrupt state"]
26pub type SWD_R = crate::BitReader;
27#[doc = "Field `SWD` writer - Clear super watch dog interrupt state"]
28pub type SWD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `BBPLL_CAL` reader - Need add desc"]
30pub type BBPLL_CAL_R = crate::BitReader;
31#[doc = "Field `BBPLL_CAL` writer - Need add desc"]
32pub type BBPLL_CAL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
35    #[inline(always)]
36    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
37        SLP_WAKEUP_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - Clear sleep reject interrupt state"]
40    #[inline(always)]
41    pub fn slp_reject(&self) -> SLP_REJECT_R {
42        SLP_REJECT_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
45    #[inline(always)]
46    pub fn wdt(&self) -> WDT_R {
47        WDT_R::new(((self.bits >> 3) & 1) != 0)
48    }
49    #[doc = "Bit 9 - Clear brown out interrupt state"]
50    #[inline(always)]
51    pub fn brown_out(&self) -> BROWN_OUT_R {
52        BROWN_OUT_R::new(((self.bits >> 9) & 1) != 0)
53    }
54    #[doc = "Bit 10 - Clear RTC main timer interrupt state"]
55    #[inline(always)]
56    pub fn main_timer(&self) -> MAIN_TIMER_R {
57        MAIN_TIMER_R::new(((self.bits >> 10) & 1) != 0)
58    }
59    #[doc = "Bit 15 - Clear super watch dog interrupt state"]
60    #[inline(always)]
61    pub fn swd(&self) -> SWD_R {
62        SWD_R::new(((self.bits >> 15) & 1) != 0)
63    }
64    #[doc = "Bit 20 - Need add desc"]
65    #[inline(always)]
66    pub fn bbpll_cal(&self) -> BBPLL_CAL_R {
67        BBPLL_CAL_R::new(((self.bits >> 20) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("INT_CLR")
74            .field("slp_wakeup", &self.slp_wakeup())
75            .field("slp_reject", &self.slp_reject())
76            .field("wdt", &self.wdt())
77            .field("brown_out", &self.brown_out())
78            .field("main_timer", &self.main_timer())
79            .field("swd", &self.swd())
80            .field("bbpll_cal", &self.bbpll_cal())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
86    #[inline(always)]
87    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
88        SLP_WAKEUP_W::new(self, 0)
89    }
90    #[doc = "Bit 1 - Clear sleep reject interrupt state"]
91    #[inline(always)]
92    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
93        SLP_REJECT_W::new(self, 1)
94    }
95    #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
96    #[inline(always)]
97    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
98        WDT_W::new(self, 3)
99    }
100    #[doc = "Bit 9 - Clear brown out interrupt state"]
101    #[inline(always)]
102    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
103        BROWN_OUT_W::new(self, 9)
104    }
105    #[doc = "Bit 10 - Clear RTC main timer interrupt state"]
106    #[inline(always)]
107    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
108        MAIN_TIMER_W::new(self, 10)
109    }
110    #[doc = "Bit 15 - Clear super watch dog interrupt state"]
111    #[inline(always)]
112    pub fn swd(&mut self) -> SWD_W<INT_CLR_SPEC> {
113        SWD_W::new(self, 15)
114    }
115    #[doc = "Bit 20 - Need add desc"]
116    #[inline(always)]
117    pub fn bbpll_cal(&mut self) -> BBPLL_CAL_W<INT_CLR_SPEC> {
118        BBPLL_CAL_W::new(self, 20)
119    }
120}
121#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct INT_CLR_SPEC;
123impl crate::RegisterSpec for INT_CLR_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
127impl crate::Readable for INT_CLR_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
129impl crate::Writable for INT_CLR_SPEC {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0010_860b;
133}
134#[doc = "`reset()` method sets INT_CLR to value 0"]
135impl crate::Resettable for INT_CLR_SPEC {
136    const RESET_VALUE: u32 = 0;
137}
esp32c2/rtc_cntl/int_clr.rs

esp32c2/rtc_cntl/
int_clr.rs
