esp32c2/rtc_cntl/
dig_pwc.rs

1#[doc = "Register `DIG_PWC` reader"]
2pub type R = crate::R<DIG_PWC_SPEC>;
3#[doc = "Register `DIG_PWC` writer"]
4pub type W = crate::W<DIG_PWC_SPEC>;
5#[doc = "Field `VDD_SPI_PWR_DRV` reader - Need add desc"]
6pub type VDD_SPI_PWR_DRV_R = crate::FieldReader;
7#[doc = "Field `VDD_SPI_PWR_DRV` writer - Need add desc"]
8pub type VDD_SPI_PWR_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `VDD_SPI_PWR_FORCE` reader - Need add desc"]
10pub type VDD_SPI_PWR_FORCE_R = crate::BitReader;
11#[doc = "Field `VDD_SPI_PWR_FORCE` writer - Need add desc"]
12pub type VDD_SPI_PWR_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `VDD_SPI_PD_EN` reader - Need add desc"]
14pub type VDD_SPI_PD_EN_R = crate::BitReader;
15#[doc = "Field `VDD_SPI_PD_EN` writer - Need add desc"]
16pub type VDD_SPI_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LSLP_MEM_FORCE_PD` reader - memories in digital core force PD in sleep"]
18pub type LSLP_MEM_FORCE_PD_R = crate::BitReader;
19#[doc = "Field `LSLP_MEM_FORCE_PD` writer - memories in digital core force PD in sleep"]
20pub type LSLP_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `LSLP_MEM_FORCE_PU` reader - memories in digital core force no PD in sleep"]
22pub type LSLP_MEM_FORCE_PU_R = crate::BitReader;
23#[doc = "Field `LSLP_MEM_FORCE_PU` writer - memories in digital core force no PD in sleep"]
24pub type LSLP_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DG_WRAP_FORCE_PD` reader - digital core force power down"]
26pub type DG_WRAP_FORCE_PD_R = crate::BitReader;
27#[doc = "Field `DG_WRAP_FORCE_PD` writer - digital core force power down"]
28pub type DG_WRAP_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DG_WRAP_FORCE_PU` reader - digital core force power up"]
30pub type DG_WRAP_FORCE_PU_R = crate::BitReader;
31#[doc = "Field `DG_WRAP_FORCE_PU` writer - digital core force power up"]
32pub type DG_WRAP_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DG_WRAP_PD_EN` reader - Need add desc"]
34pub type DG_WRAP_PD_EN_R = crate::BitReader;
35#[doc = "Field `DG_WRAP_PD_EN` writer - Need add desc"]
36pub type DG_WRAP_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bits 0:1 - Need add desc"]
39    #[inline(always)]
40    pub fn vdd_spi_pwr_drv(&self) -> VDD_SPI_PWR_DRV_R {
41        VDD_SPI_PWR_DRV_R::new((self.bits & 3) as u8)
42    }
43    #[doc = "Bit 2 - Need add desc"]
44    #[inline(always)]
45    pub fn vdd_spi_pwr_force(&self) -> VDD_SPI_PWR_FORCE_R {
46        VDD_SPI_PWR_FORCE_R::new(((self.bits >> 2) & 1) != 0)
47    }
48    #[doc = "Bit 3 - Need add desc"]
49    #[inline(always)]
50    pub fn vdd_spi_pd_en(&self) -> VDD_SPI_PD_EN_R {
51        VDD_SPI_PD_EN_R::new(((self.bits >> 3) & 1) != 0)
52    }
53    #[doc = "Bit 4 - memories in digital core force PD in sleep"]
54    #[inline(always)]
55    pub fn lslp_mem_force_pd(&self) -> LSLP_MEM_FORCE_PD_R {
56        LSLP_MEM_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0)
57    }
58    #[doc = "Bit 5 - memories in digital core force no PD in sleep"]
59    #[inline(always)]
60    pub fn lslp_mem_force_pu(&self) -> LSLP_MEM_FORCE_PU_R {
61        LSLP_MEM_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0)
62    }
63    #[doc = "Bit 19 - digital core force power down"]
64    #[inline(always)]
65    pub fn dg_wrap_force_pd(&self) -> DG_WRAP_FORCE_PD_R {
66        DG_WRAP_FORCE_PD_R::new(((self.bits >> 19) & 1) != 0)
67    }
68    #[doc = "Bit 20 - digital core force power up"]
69    #[inline(always)]
70    pub fn dg_wrap_force_pu(&self) -> DG_WRAP_FORCE_PU_R {
71        DG_WRAP_FORCE_PU_R::new(((self.bits >> 20) & 1) != 0)
72    }
73    #[doc = "Bit 31 - Need add desc"]
74    #[inline(always)]
75    pub fn dg_wrap_pd_en(&self) -> DG_WRAP_PD_EN_R {
76        DG_WRAP_PD_EN_R::new(((self.bits >> 31) & 1) != 0)
77    }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82        f.debug_struct("DIG_PWC")
83            .field("vdd_spi_pwr_drv", &self.vdd_spi_pwr_drv())
84            .field("vdd_spi_pwr_force", &self.vdd_spi_pwr_force())
85            .field("vdd_spi_pd_en", &self.vdd_spi_pd_en())
86            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
87            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
88            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
89            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
90            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
91            .finish()
92    }
93}
94impl W {
95    #[doc = "Bits 0:1 - Need add desc"]
96    #[inline(always)]
97    pub fn vdd_spi_pwr_drv(&mut self) -> VDD_SPI_PWR_DRV_W<DIG_PWC_SPEC> {
98        VDD_SPI_PWR_DRV_W::new(self, 0)
99    }
100    #[doc = "Bit 2 - Need add desc"]
101    #[inline(always)]
102    pub fn vdd_spi_pwr_force(&mut self) -> VDD_SPI_PWR_FORCE_W<DIG_PWC_SPEC> {
103        VDD_SPI_PWR_FORCE_W::new(self, 2)
104    }
105    #[doc = "Bit 3 - Need add desc"]
106    #[inline(always)]
107    pub fn vdd_spi_pd_en(&mut self) -> VDD_SPI_PD_EN_W<DIG_PWC_SPEC> {
108        VDD_SPI_PD_EN_W::new(self, 3)
109    }
110    #[doc = "Bit 4 - memories in digital core force PD in sleep"]
111    #[inline(always)]
112    pub fn lslp_mem_force_pd(&mut self) -> LSLP_MEM_FORCE_PD_W<DIG_PWC_SPEC> {
113        LSLP_MEM_FORCE_PD_W::new(self, 4)
114    }
115    #[doc = "Bit 5 - memories in digital core force no PD in sleep"]
116    #[inline(always)]
117    pub fn lslp_mem_force_pu(&mut self) -> LSLP_MEM_FORCE_PU_W<DIG_PWC_SPEC> {
118        LSLP_MEM_FORCE_PU_W::new(self, 5)
119    }
120    #[doc = "Bit 19 - digital core force power down"]
121    #[inline(always)]
122    pub fn dg_wrap_force_pd(&mut self) -> DG_WRAP_FORCE_PD_W<DIG_PWC_SPEC> {
123        DG_WRAP_FORCE_PD_W::new(self, 19)
124    }
125    #[doc = "Bit 20 - digital core force power up"]
126    #[inline(always)]
127    pub fn dg_wrap_force_pu(&mut self) -> DG_WRAP_FORCE_PU_W<DIG_PWC_SPEC> {
128        DG_WRAP_FORCE_PU_W::new(self, 20)
129    }
130    #[doc = "Bit 31 - Need add desc"]
131    #[inline(always)]
132    pub fn dg_wrap_pd_en(&mut self) -> DG_WRAP_PD_EN_W<DIG_PWC_SPEC> {
133        DG_WRAP_PD_EN_W::new(self, 31)
134    }
135}
136#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dig_pwc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dig_pwc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct DIG_PWC_SPEC;
138impl crate::RegisterSpec for DIG_PWC_SPEC {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [`dig_pwc::R`](R) reader structure"]
142impl crate::Readable for DIG_PWC_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`dig_pwc::W`](W) writer structure"]
144impl crate::Writable for DIG_PWC_SPEC {
145    type Safety = crate::Unsafe;
146    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets DIG_PWC to value 0x0010_0020"]
150impl crate::Resettable for DIG_PWC_SPEC {
151    const RESET_VALUE: u32 = 0x0010_0020;
152}
esp32c2/rtc_cntl/dig_pwc.rs

esp32c2/rtc_cntl/
dig_pwc.rs
