esp32c2/ledc/timer/
conf.rs

1#[doc = "Register `CONF` reader"]
2pub type R = crate::R<CONF_SPEC>;
3#[doc = "Register `CONF` writer"]
4pub type W = crate::W<CONF_SPEC>;
5#[doc = "Field `DUTY_RES` reader - This register is used to control the range of the counter in timer %s."]
6pub type DUTY_RES_R = crate::FieldReader;
7#[doc = "Field `DUTY_RES` writer - This register is used to control the range of the counter in timer %s."]
8pub type DUTY_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `CLK_DIV` reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
10pub type CLK_DIV_R = crate::FieldReader<u32>;
11#[doc = "Field `CLK_DIV` writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
12pub type CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
13#[doc = "Field `PAUSE` reader - This bit is used to suspend the counter in timer %s."]
14pub type PAUSE_R = crate::BitReader;
15#[doc = "Field `PAUSE` writer - This bit is used to suspend the counter in timer %s."]
16pub type PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RST` reader - This bit is used to reset timer %s. The counter will show 0 after reset."]
18pub type RST_R = crate::BitReader;
19#[doc = "Field `RST` writer - This bit is used to reset timer %s. The counter will show 0 after reset."]
20pub type RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TICK_SEL` reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
22pub type TICK_SEL_R = crate::BitReader;
23#[doc = "Field `TICK_SEL` writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
24pub type TICK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PARA_UP` writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."]
26pub type PARA_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl R {
28    #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
29    #[inline(always)]
30    pub fn duty_res(&self) -> DUTY_RES_R {
31        DUTY_RES_R::new((self.bits & 0x0f) as u8)
32    }
33    #[doc = "Bits 4:21 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
34    #[inline(always)]
35    pub fn clk_div(&self) -> CLK_DIV_R {
36        CLK_DIV_R::new((self.bits >> 4) & 0x0003_ffff)
37    }
38    #[doc = "Bit 22 - This bit is used to suspend the counter in timer %s."]
39    #[inline(always)]
40    pub fn pause(&self) -> PAUSE_R {
41        PAUSE_R::new(((self.bits >> 22) & 1) != 0)
42    }
43    #[doc = "Bit 23 - This bit is used to reset timer %s. The counter will show 0 after reset."]
44    #[inline(always)]
45    pub fn rst(&self) -> RST_R {
46        RST_R::new(((self.bits >> 23) & 1) != 0)
47    }
48    #[doc = "Bit 24 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
49    #[inline(always)]
50    pub fn tick_sel(&self) -> TICK_SEL_R {
51        TICK_SEL_R::new(((self.bits >> 24) & 1) != 0)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("CONF")
58            .field("duty_res", &self.duty_res())
59            .field("clk_div", &self.clk_div())
60            .field("pause", &self.pause())
61            .field("rst", &self.rst())
62            .field("tick_sel", &self.tick_sel())
63            .finish()
64    }
65}
66impl W {
67    #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
68    #[inline(always)]
69    pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
70        DUTY_RES_W::new(self, 0)
71    }
72    #[doc = "Bits 4:21 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
73    #[inline(always)]
74    pub fn clk_div(&mut self) -> CLK_DIV_W<CONF_SPEC> {
75        CLK_DIV_W::new(self, 4)
76    }
77    #[doc = "Bit 22 - This bit is used to suspend the counter in timer %s."]
78    #[inline(always)]
79    pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
80        PAUSE_W::new(self, 22)
81    }
82    #[doc = "Bit 23 - This bit is used to reset timer %s. The counter will show 0 after reset."]
83    #[inline(always)]
84    pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
85        RST_W::new(self, 23)
86    }
87    #[doc = "Bit 24 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
88    #[inline(always)]
89    pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
90        TICK_SEL_W::new(self, 24)
91    }
92    #[doc = "Bit 25 - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."]
93    #[inline(always)]
94    pub fn para_up(&mut self) -> PARA_UP_W<CONF_SPEC> {
95        PARA_UP_W::new(self, 25)
96    }
97}
98#[doc = "Timer 0 configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct CONF_SPEC;
100impl crate::RegisterSpec for CONF_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
104impl crate::Readable for CONF_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
106impl crate::Writable for CONF_SPEC {
107    type Safety = crate::Unsafe;
108    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
109    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110}
111#[doc = "`reset()` method sets CONF to value 0x0080_0000"]
112impl crate::Resettable for CONF_SPEC {
113    const RESET_VALUE: u32 = 0x0080_0000;
114}
esp32c2/ledc/timer/conf.rs

esp32c2/ledc/timer/
conf.rs
