esp32c2/i2c0/
scl_start_hold.rs

1#[doc = "Register `SCL_START_HOLD` reader"]
2pub type R = crate::R<SCL_START_HOLD_SPEC>;
3#[doc = "Register `SCL_START_HOLD` writer"]
4pub type W = crate::W<SCL_START_HOLD_SPEC>;
5#[doc = "Field `TIME` reader - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
6pub type TIME_R = crate::FieldReader<u16>;
7#[doc = "Field `TIME` writer - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
8pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9impl R {
10    #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
11    #[inline(always)]
12    pub fn time(&self) -> TIME_R {
13        TIME_R::new((self.bits & 0x01ff) as u16)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("SCL_START_HOLD")
20            .field("time", &self.time())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
26    #[inline(always)]
27    pub fn time(&mut self) -> TIME_W<SCL_START_HOLD_SPEC> {
28        TIME_W::new(self, 0)
29    }
30}
31#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_start_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_start_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct SCL_START_HOLD_SPEC;
33impl crate::RegisterSpec for SCL_START_HOLD_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`scl_start_hold::R`](R) reader structure"]
37impl crate::Readable for SCL_START_HOLD_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`scl_start_hold::W`](W) writer structure"]
39impl crate::Writable for SCL_START_HOLD_SPEC {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets SCL_START_HOLD to value 0x08"]
45impl crate::Resettable for SCL_START_HOLD_SPEC {
46    const RESET_VALUE: u32 = 0x08;
47}
esp32c2/i2c0/scl_start_hold.rs

esp32c2/i2c0/
scl_start_hold.rs
