1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `RXFIFO_WM` reader - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."]
4pub type RXFIFO_WM_R = crate::BitReader;
5#[doc = "Field `TXFIFO_WM` reader - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."]
6pub type TXFIFO_WM_R = crate::BitReader;
7#[doc = "Field `RXFIFO_OVF` reader - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."]
8pub type RXFIFO_OVF_R = crate::BitReader;
9#[doc = "Field `END_DETECT` reader - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."]
10pub type END_DETECT_R = crate::BitReader;
11#[doc = "Field `BYTE_TRANS_DONE` reader - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."]
12pub type BYTE_TRANS_DONE_R = crate::BitReader;
13#[doc = "Field `ARBITRATION_LOST` reader - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."]
14pub type ARBITRATION_LOST_R = crate::BitReader;
15#[doc = "Field `MST_TXFIFO_UDF` reader - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."]
16pub type MST_TXFIFO_UDF_R = crate::BitReader;
17#[doc = "Field `TRANS_COMPLETE` reader - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."]
18pub type TRANS_COMPLETE_R = crate::BitReader;
19#[doc = "Field `TIME_OUT` reader - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."]
20pub type TIME_OUT_R = crate::BitReader;
21#[doc = "Field `TRANS_START` reader - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."]
22pub type TRANS_START_R = crate::BitReader;
23#[doc = "Field `NACK` reader - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."]
24pub type NACK_R = crate::BitReader;
25#[doc = "Field `TXFIFO_OVF` reader - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."]
26pub type TXFIFO_OVF_R = crate::BitReader;
27#[doc = "Field `RXFIFO_UDF` reader - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."]
28pub type RXFIFO_UDF_R = crate::BitReader;
29#[doc = "Field `SCL_ST_TO` reader - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."]
30pub type SCL_ST_TO_R = crate::BitReader;
31#[doc = "Field `SCL_MAIN_ST_TO` reader - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
32pub type SCL_MAIN_ST_TO_R = crate::BitReader;
33#[doc = "Field `DET_START` reader - The raw interrupt bit for I2C_DET_START_INT interrupt."]
34pub type DET_START_R = crate::BitReader;
35impl R {
36 #[doc = "Bit 0 - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."]
37 #[inline(always)]
38 pub fn rxfifo_wm(&self) -> RXFIFO_WM_R {
39 RXFIFO_WM_R::new((self.bits & 1) != 0)
40 }
41 #[doc = "Bit 1 - The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt."]
42 #[inline(always)]
43 pub fn txfifo_wm(&self) -> TXFIFO_WM_R {
44 TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0)
45 }
46 #[doc = "Bit 2 - The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt."]
47 #[inline(always)]
48 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
49 RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0)
50 }
51 #[doc = "Bit 3 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."]
52 #[inline(always)]
53 pub fn end_detect(&self) -> END_DETECT_R {
54 END_DETECT_R::new(((self.bits >> 3) & 1) != 0)
55 }
56 #[doc = "Bit 4 - The raw interrupt bit for the I2C_END_DETECT_INT interrupt."]
57 #[inline(always)]
58 pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R {
59 BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0)
60 }
61 #[doc = "Bit 5 - The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt."]
62 #[inline(always)]
63 pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
64 ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
65 }
66 #[doc = "Bit 6 - The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt."]
67 #[inline(always)]
68 pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R {
69 MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0)
70 }
71 #[doc = "Bit 7 - The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt."]
72 #[inline(always)]
73 pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
74 TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
75 }
76 #[doc = "Bit 8 - The raw interrupt bit for the I2C_TIME_OUT_INT interrupt."]
77 #[inline(always)]
78 pub fn time_out(&self) -> TIME_OUT_R {
79 TIME_OUT_R::new(((self.bits >> 8) & 1) != 0)
80 }
81 #[doc = "Bit 9 - The raw interrupt bit for the I2C_TRANS_START_INT interrupt."]
82 #[inline(always)]
83 pub fn trans_start(&self) -> TRANS_START_R {
84 TRANS_START_R::new(((self.bits >> 9) & 1) != 0)
85 }
86 #[doc = "Bit 10 - The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt."]
87 #[inline(always)]
88 pub fn nack(&self) -> NACK_R {
89 NACK_R::new(((self.bits >> 10) & 1) != 0)
90 }
91 #[doc = "Bit 11 - The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt."]
92 #[inline(always)]
93 pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R {
94 TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0)
95 }
96 #[doc = "Bit 12 - The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt."]
97 #[inline(always)]
98 pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R {
99 RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0)
100 }
101 #[doc = "Bit 13 - The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt."]
102 #[inline(always)]
103 pub fn scl_st_to(&self) -> SCL_ST_TO_R {
104 SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0)
105 }
106 #[doc = "Bit 14 - The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
107 #[inline(always)]
108 pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R {
109 SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0)
110 }
111 #[doc = "Bit 15 - The raw interrupt bit for I2C_DET_START_INT interrupt."]
112 #[inline(always)]
113 pub fn det_start(&self) -> DET_START_R {
114 DET_START_R::new(((self.bits >> 15) & 1) != 0)
115 }
116}
117#[cfg(feature = "impl-register-debug")]
118impl core::fmt::Debug for R {
119 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
120 f.debug_struct("INT_RAW")
121 .field("rxfifo_wm", &self.rxfifo_wm())
122 .field("txfifo_wm", &self.txfifo_wm())
123 .field("rxfifo_ovf", &self.rxfifo_ovf())
124 .field("end_detect", &self.end_detect())
125 .field("byte_trans_done", &self.byte_trans_done())
126 .field("arbitration_lost", &self.arbitration_lost())
127 .field("mst_txfifo_udf", &self.mst_txfifo_udf())
128 .field("trans_complete", &self.trans_complete())
129 .field("time_out", &self.time_out())
130 .field("trans_start", &self.trans_start())
131 .field("nack", &self.nack())
132 .field("txfifo_ovf", &self.txfifo_ovf())
133 .field("rxfifo_udf", &self.rxfifo_udf())
134 .field("scl_st_to", &self.scl_st_to())
135 .field("scl_main_st_to", &self.scl_main_st_to())
136 .field("det_start", &self.det_start())
137 .finish()
138 }
139}
140#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
141pub struct INT_RAW_SPEC;
142impl crate::RegisterSpec for INT_RAW_SPEC {
143 type Ux = u32;
144}
145#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
146impl crate::Readable for INT_RAW_SPEC {}
147#[doc = "`reset()` method sets INT_RAW to value 0x02"]
148impl crate::Resettable for INT_RAW_SPEC {
149 const RESET_VALUE: u32 = 0x02;
150}