esp32c2/i2c0/
fifo_conf.rs1#[doc = "Register `FIFO_CONF` reader"]
2pub type R = crate::R<FIFO_CONF_SPEC>;
3#[doc = "Register `FIFO_CONF` writer"]
4pub type W = crate::W<FIFO_CONF_SPEC>;
5#[doc = "Field `RXFIFO_WM_THRHD` reader - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
6pub type RXFIFO_WM_THRHD_R = crate::FieldReader;
7#[doc = "Field `RXFIFO_WM_THRHD` writer - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
8pub type RXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `TXFIFO_WM_THRHD` reader - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."]
10pub type TXFIFO_WM_THRHD_R = crate::FieldReader;
11#[doc = "Field `TXFIFO_WM_THRHD` writer - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."]
12pub type TXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `NONFIFO_EN` reader - Set this bit to enable APB nonfifo access."]
14pub type NONFIFO_EN_R = crate::BitReader;
15#[doc = "Field `NONFIFO_EN` writer - Set this bit to enable APB nonfifo access."]
16pub type NONFIFO_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_FIFO_RST` reader - Set this bit to reset rx-fifo."]
18pub type RX_FIFO_RST_R = crate::BitReader;
19#[doc = "Field `RX_FIFO_RST` writer - Set this bit to reset rx-fifo."]
20pub type RX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_FIFO_RST` reader - Set this bit to reset tx-fifo."]
22pub type TX_FIFO_RST_R = crate::BitReader;
23#[doc = "Field `TX_FIFO_RST` writer - Set this bit to reset tx-fifo."]
24pub type TX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FIFO_PRT_EN` reader - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty."]
26pub type FIFO_PRT_EN_R = crate::BitReader;
27#[doc = "Field `FIFO_PRT_EN` writer - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty."]
28pub type FIFO_PRT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30 #[doc = "Bits 0:3 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
31 #[inline(always)]
32 pub fn rxfifo_wm_thrhd(&self) -> RXFIFO_WM_THRHD_R {
33 RXFIFO_WM_THRHD_R::new((self.bits & 0x0f) as u8)
34 }
35 #[doc = "Bits 5:8 - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."]
36 #[inline(always)]
37 pub fn txfifo_wm_thrhd(&self) -> TXFIFO_WM_THRHD_R {
38 TXFIFO_WM_THRHD_R::new(((self.bits >> 5) & 0x0f) as u8)
39 }
40 #[doc = "Bit 10 - Set this bit to enable APB nonfifo access."]
41 #[inline(always)]
42 pub fn nonfifo_en(&self) -> NONFIFO_EN_R {
43 NONFIFO_EN_R::new(((self.bits >> 10) & 1) != 0)
44 }
45 #[doc = "Bit 12 - Set this bit to reset rx-fifo."]
46 #[inline(always)]
47 pub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R {
48 RX_FIFO_RST_R::new(((self.bits >> 12) & 1) != 0)
49 }
50 #[doc = "Bit 13 - Set this bit to reset tx-fifo."]
51 #[inline(always)]
52 pub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R {
53 TX_FIFO_RST_R::new(((self.bits >> 13) & 1) != 0)
54 }
55 #[doc = "Bit 14 - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty."]
56 #[inline(always)]
57 pub fn fifo_prt_en(&self) -> FIFO_PRT_EN_R {
58 FIFO_PRT_EN_R::new(((self.bits >> 14) & 1) != 0)
59 }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64 f.debug_struct("FIFO_CONF")
65 .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
66 .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
67 .field("nonfifo_en", &self.nonfifo_en())
68 .field("rx_fifo_rst", &self.rx_fifo_rst())
69 .field("tx_fifo_rst", &self.tx_fifo_rst())
70 .field("fifo_prt_en", &self.fifo_prt_en())
71 .finish()
72 }
73}
74impl W {
75 #[doc = "Bits 0:3 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
76 #[inline(always)]
77 pub fn rxfifo_wm_thrhd(&mut self) -> RXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
78 RXFIFO_WM_THRHD_W::new(self, 0)
79 }
80 #[doc = "Bits 5:8 - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."]
81 #[inline(always)]
82 pub fn txfifo_wm_thrhd(&mut self) -> TXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
83 TXFIFO_WM_THRHD_W::new(self, 5)
84 }
85 #[doc = "Bit 10 - Set this bit to enable APB nonfifo access."]
86 #[inline(always)]
87 pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W<FIFO_CONF_SPEC> {
88 NONFIFO_EN_W::new(self, 10)
89 }
90 #[doc = "Bit 12 - Set this bit to reset rx-fifo."]
91 #[inline(always)]
92 pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W<FIFO_CONF_SPEC> {
93 RX_FIFO_RST_W::new(self, 12)
94 }
95 #[doc = "Bit 13 - Set this bit to reset tx-fifo."]
96 #[inline(always)]
97 pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<FIFO_CONF_SPEC> {
98 TX_FIFO_RST_W::new(self, 13)
99 }
100 #[doc = "Bit 14 - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty."]
101 #[inline(always)]
102 pub fn fifo_prt_en(&mut self) -> FIFO_PRT_EN_W<FIFO_CONF_SPEC> {
103 FIFO_PRT_EN_W::new(self, 14)
104 }
105}
106#[doc = "FIFO configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct FIFO_CONF_SPEC;
108impl crate::RegisterSpec for FIFO_CONF_SPEC {
109 type Ux = u32;
110}
111#[doc = "`read()` method returns [`fifo_conf::R`](R) reader structure"]
112impl crate::Readable for FIFO_CONF_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`fifo_conf::W`](W) writer structure"]
114impl crate::Writable for FIFO_CONF_SPEC {
115 type Safety = crate::Unsafe;
116 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets FIFO_CONF to value 0x4046"]
120impl crate::Resettable for FIFO_CONF_SPEC {
121 const RESET_VALUE: u32 = 0x4046;
122}