esp32c2/i2c0/
clk_conf.rs

1#[doc = "Register `CLK_CONF` reader"]
2pub type R = crate::R<CLK_CONF_SPEC>;
3#[doc = "Register `CLK_CONF` writer"]
4pub type W = crate::W<CLK_CONF_SPEC>;
5#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor for i2c module"]
6pub type SCLK_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor for i2c module"]
8pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor for i2c module"]
10pub type SCLK_DIV_A_R = crate::FieldReader;
11#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor for i2c module"]
12pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor for i2c module"]
14pub type SCLK_DIV_B_R = crate::FieldReader;
15#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor for i2c module"]
16pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `SCLK_SEL` reader - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
18pub type SCLK_SEL_R = crate::BitReader;
19#[doc = "Field `SCLK_SEL` writer - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
20pub type SCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SCLK_ACTIVE` reader - The clock switch for i2c module"]
22pub type SCLK_ACTIVE_R = crate::BitReader;
23#[doc = "Field `SCLK_ACTIVE` writer - The clock switch for i2c module"]
24pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
27    #[inline(always)]
28    pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R {
29        SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8)
30    }
31    #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"]
32    #[inline(always)]
33    pub fn sclk_div_a(&self) -> SCLK_DIV_A_R {
34        SCLK_DIV_A_R::new(((self.bits >> 8) & 0x3f) as u8)
35    }
36    #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"]
37    #[inline(always)]
38    pub fn sclk_div_b(&self) -> SCLK_DIV_B_R {
39        SCLK_DIV_B_R::new(((self.bits >> 14) & 0x3f) as u8)
40    }
41    #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
42    #[inline(always)]
43    pub fn sclk_sel(&self) -> SCLK_SEL_R {
44        SCLK_SEL_R::new(((self.bits >> 20) & 1) != 0)
45    }
46    #[doc = "Bit 21 - The clock switch for i2c module"]
47    #[inline(always)]
48    pub fn sclk_active(&self) -> SCLK_ACTIVE_R {
49        SCLK_ACTIVE_R::new(((self.bits >> 21) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("CLK_CONF")
56            .field("sclk_div_num", &self.sclk_div_num())
57            .field("sclk_div_a", &self.sclk_div_a())
58            .field("sclk_div_b", &self.sclk_div_b())
59            .field("sclk_sel", &self.sclk_sel())
60            .field("sclk_active", &self.sclk_active())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
66    #[inline(always)]
67    pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<CLK_CONF_SPEC> {
68        SCLK_DIV_NUM_W::new(self, 0)
69    }
70    #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"]
71    #[inline(always)]
72    pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<CLK_CONF_SPEC> {
73        SCLK_DIV_A_W::new(self, 8)
74    }
75    #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"]
76    #[inline(always)]
77    pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<CLK_CONF_SPEC> {
78        SCLK_DIV_B_W::new(self, 14)
79    }
80    #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."]
81    #[inline(always)]
82    pub fn sclk_sel(&mut self) -> SCLK_SEL_W<CLK_CONF_SPEC> {
83        SCLK_SEL_W::new(self, 20)
84    }
85    #[doc = "Bit 21 - The clock switch for i2c module"]
86    #[inline(always)]
87    pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<CLK_CONF_SPEC> {
88        SCLK_ACTIVE_W::new(self, 21)
89    }
90}
91#[doc = "I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct CLK_CONF_SPEC;
93impl crate::RegisterSpec for CLK_CONF_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
97impl crate::Readable for CLK_CONF_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
99impl crate::Writable for CLK_CONF_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets CLK_CONF to value 0x0020_0000"]
105impl crate::Resettable for CLK_CONF_SPEC {
106    const RESET_VALUE: u32 = 0x0020_0000;
107}
esp32c2/i2c0/clk_conf.rs

esp32c2/i2c0/
clk_conf.rs
