esp32c2/extmem/
icache_sync_ctrl.rs

1#[doc = "Register `ICACHE_SYNC_CTRL` reader"]
2pub type R = crate::R<ICACHE_SYNC_CTRL_SPEC>;
3#[doc = "Register `ICACHE_SYNC_CTRL` writer"]
4pub type W = crate::W<ICACHE_SYNC_CTRL_SPEC>;
5#[doc = "Field `ICACHE_INVALIDATE_ENA` reader - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
6pub type ICACHE_INVALIDATE_ENA_R = crate::BitReader;
7#[doc = "Field `ICACHE_INVALIDATE_ENA` writer - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
8pub type ICACHE_INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ICACHE_SYNC_DONE` reader - The bit is used to indicate invalidate operation is finished."]
10pub type ICACHE_SYNC_DONE_R = crate::BitReader;
11impl R {
12    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
13    #[inline(always)]
14    pub fn icache_invalidate_ena(&self) -> ICACHE_INVALIDATE_ENA_R {
15        ICACHE_INVALIDATE_ENA_R::new((self.bits & 1) != 0)
16    }
17    #[doc = "Bit 1 - The bit is used to indicate invalidate operation is finished."]
18    #[inline(always)]
19    pub fn icache_sync_done(&self) -> ICACHE_SYNC_DONE_R {
20        ICACHE_SYNC_DONE_R::new(((self.bits >> 1) & 1) != 0)
21    }
22}
23#[cfg(feature = "impl-register-debug")]
24impl core::fmt::Debug for R {
25    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
26        f.debug_struct("ICACHE_SYNC_CTRL")
27            .field("icache_invalidate_ena", &self.icache_invalidate_ena())
28            .field("icache_sync_done", &self.icache_sync_done())
29            .finish()
30    }
31}
32impl W {
33    #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
34    #[inline(always)]
35    pub fn icache_invalidate_ena(&mut self) -> ICACHE_INVALIDATE_ENA_W<ICACHE_SYNC_CTRL_SPEC> {
36        ICACHE_INVALIDATE_ENA_W::new(self, 0)
37    }
38}
39#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_sync_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_sync_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
40pub struct ICACHE_SYNC_CTRL_SPEC;
41impl crate::RegisterSpec for ICACHE_SYNC_CTRL_SPEC {
42    type Ux = u32;
43}
44#[doc = "`read()` method returns [`icache_sync_ctrl::R`](R) reader structure"]
45impl crate::Readable for ICACHE_SYNC_CTRL_SPEC {}
46#[doc = "`write(|w| ..)` method takes [`icache_sync_ctrl::W`](W) writer structure"]
47impl crate::Writable for ICACHE_SYNC_CTRL_SPEC {
48    type Safety = crate::Unsafe;
49    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
50    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
51}
52#[doc = "`reset()` method sets ICACHE_SYNC_CTRL to value 0x01"]
53impl crate::Resettable for ICACHE_SYNC_CTRL_SPEC {
54    const RESET_VALUE: u32 = 0x01;
55}
esp32c2/extmem/icache_sync_ctrl.rs

esp32c2/extmem/
icache_sync_ctrl.rs
