Module esp32c2::ledc::timer_conf
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Timer %s configuration
Structs
Type Definitions
Field
CLK_DIV reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.Field
CLK_DIV writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.Field
DUTY_RES reader - This register is used to control the range of the counter in timer %s.Field
DUTY_RES writer - This register is used to control the range of the counter in timer %s.Field
PARA_UP writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.Field
PAUSE reader - This bit is used to suspend the counter in timer %s.Field
PAUSE writer - This bit is used to suspend the counter in timer %s.Field
RST reader - This bit is used to reset timer %s. The counter will show 0 after reset.Field
RST writer - This bit is used to reset timer %s. The counter will show 0 after reset.Field
TICK_SEL reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICKField
TICK_SEL writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICK