esp32c2/rtc_cntl/
slow_clk_conf.rs

1#[doc = "Register `SLOW_CLK_CONF` reader"]
2pub type R = crate::R<SLOW_CLK_CONF_SPEC>;
3#[doc = "Register `SLOW_CLK_CONF` writer"]
4pub type W = crate::W<SLOW_CLK_CONF_SPEC>;
5#[doc = "Field `ANA_CLK_DIV_VLD` reader - used to sync div bus. clear vld before set reg_rtc_ana_clk_div"]
6pub type ANA_CLK_DIV_VLD_R = crate::BitReader;
7#[doc = "Field `ANA_CLK_DIV_VLD` writer - used to sync div bus. clear vld before set reg_rtc_ana_clk_div"]
8pub type ANA_CLK_DIV_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ANA_CLK_DIV` reader - Need add desc"]
10pub type ANA_CLK_DIV_R = crate::FieldReader;
11#[doc = "Field `ANA_CLK_DIV` writer - Need add desc"]
12pub type ANA_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SLOW_CLK_NEXT_EDGE` reader - Need add desc"]
14pub type SLOW_CLK_NEXT_EDGE_R = crate::BitReader;
15#[doc = "Field `SLOW_CLK_NEXT_EDGE` writer - Need add desc"]
16pub type SLOW_CLK_NEXT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div"]
19    #[inline(always)]
20    pub fn ana_clk_div_vld(&self) -> ANA_CLK_DIV_VLD_R {
21        ANA_CLK_DIV_VLD_R::new(((self.bits >> 22) & 1) != 0)
22    }
23    #[doc = "Bits 23:30 - Need add desc"]
24    #[inline(always)]
25    pub fn ana_clk_div(&self) -> ANA_CLK_DIV_R {
26        ANA_CLK_DIV_R::new(((self.bits >> 23) & 0xff) as u8)
27    }
28    #[doc = "Bit 31 - Need add desc"]
29    #[inline(always)]
30    pub fn slow_clk_next_edge(&self) -> SLOW_CLK_NEXT_EDGE_R {
31        SLOW_CLK_NEXT_EDGE_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("SLOW_CLK_CONF")
38            .field("ana_clk_div_vld", &self.ana_clk_div_vld())
39            .field("ana_clk_div", &self.ana_clk_div())
40            .field("slow_clk_next_edge", &self.slow_clk_next_edge())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div"]
46    #[inline(always)]
47    pub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<SLOW_CLK_CONF_SPEC> {
48        ANA_CLK_DIV_VLD_W::new(self, 22)
49    }
50    #[doc = "Bits 23:30 - Need add desc"]
51    #[inline(always)]
52    pub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<SLOW_CLK_CONF_SPEC> {
53        ANA_CLK_DIV_W::new(self, 23)
54    }
55    #[doc = "Bit 31 - Need add desc"]
56    #[inline(always)]
57    pub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<SLOW_CLK_CONF_SPEC> {
58        SLOW_CLK_NEXT_EDGE_W::new(self, 31)
59    }
60}
61#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`slow_clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slow_clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct SLOW_CLK_CONF_SPEC;
63impl crate::RegisterSpec for SLOW_CLK_CONF_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`slow_clk_conf::R`](R) reader structure"]
67impl crate::Readable for SLOW_CLK_CONF_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`slow_clk_conf::W`](W) writer structure"]
69impl crate::Writable for SLOW_CLK_CONF_SPEC {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets SLOW_CLK_CONF to value 0x0040_0000"]
73impl crate::Resettable for SLOW_CLK_CONF_SPEC {
74    const RESET_VALUE: u32 = 0x0040_0000;
75}
esp32c2/rtc_cntl/slow_clk_conf.rs

esp32c2/rtc_cntl/
slow_clk_conf.rs
