esp32c2/
interrupt_core0.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    core_0_intr_map: [CORE_0_INTR_MAP; 42],
6    _reserved1: [u8; 0x04],
7    core_0_intr_status: [CORE_0_INTR_STATUS; 2],
8    clock_gate: CLOCK_GATE,
9    cpu_int_enable: CPU_INT_ENABLE,
10    cpu_int_type: CPU_INT_TYPE,
11    cpu_int_clear: CPU_INT_CLEAR,
12    cpu_int_eip_status: CPU_INT_EIP_STATUS,
13    cpu_int_pri: [CPU_INT_PRI; 32],
14    cpu_int_thresh: CPU_INT_THRESH,
15    _reserved9: [u8; 0x06b0],
16    interrupt_reg_date: INTERRUPT_REG_DATE,
17}
18impl RegisterBlock {
19    #[doc = "0x00..0xa8 - "]
20    #[inline(always)]
21    pub const fn core_0_intr_map(&self, n: usize) -> &CORE_0_INTR_MAP {
22        &self.core_0_intr_map[n]
23    }
24    #[doc = "Iterator for array of:"]
25    #[doc = "0x00..0xa8 - "]
26    #[inline(always)]
27    pub fn core_0_intr_map_iter(&self) -> impl Iterator<Item = &CORE_0_INTR_MAP> {
28        self.core_0_intr_map.iter()
29    }
30    #[doc = "0xac..0xb4 - register description"]
31    #[doc = ""]
32    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `CORE_0_INTR_STATUSREG_0` register.</div>"]
33    #[inline(always)]
34    pub const fn core_0_intr_status(&self, n: usize) -> &CORE_0_INTR_STATUS {
35        &self.core_0_intr_status[n]
36    }
37    #[doc = "Iterator for array of:"]
38    #[doc = "0xac..0xb4 - register description"]
39    #[inline(always)]
40    pub fn core_0_intr_status_iter(&self) -> impl Iterator<Item = &CORE_0_INTR_STATUS> {
41        self.core_0_intr_status.iter()
42    }
43    #[doc = "0xac - register description"]
44    #[inline(always)]
45    pub const fn core_0_intr_statusreg_0(&self) -> &CORE_0_INTR_STATUS {
46        self.core_0_intr_status(0)
47    }
48    #[doc = "0xb0 - register description"]
49    #[inline(always)]
50    pub const fn core_0_intr_statusreg_1(&self) -> &CORE_0_INTR_STATUS {
51        self.core_0_intr_status(1)
52    }
53    #[doc = "0xb4 - register description"]
54    #[inline(always)]
55    pub const fn clock_gate(&self) -> &CLOCK_GATE {
56        &self.clock_gate
57    }
58    #[doc = "0xb8 - register description"]
59    #[inline(always)]
60    pub const fn cpu_int_enable(&self) -> &CPU_INT_ENABLE {
61        &self.cpu_int_enable
62    }
63    #[doc = "0xbc - register description"]
64    #[inline(always)]
65    pub const fn cpu_int_type(&self) -> &CPU_INT_TYPE {
66        &self.cpu_int_type
67    }
68    #[doc = "0xc0 - register description"]
69    #[inline(always)]
70    pub const fn cpu_int_clear(&self) -> &CPU_INT_CLEAR {
71        &self.cpu_int_clear
72    }
73    #[doc = "0xc4 - register description"]
74    #[inline(always)]
75    pub const fn cpu_int_eip_status(&self) -> &CPU_INT_EIP_STATUS {
76        &self.cpu_int_eip_status
77    }
78    #[doc = "0xc8..0x148 - register description"]
79    #[inline(always)]
80    pub const fn cpu_int_pri(&self, n: usize) -> &CPU_INT_PRI {
81        &self.cpu_int_pri[n]
82    }
83    #[doc = "Iterator for array of:"]
84    #[doc = "0xc8..0x148 - register description"]
85    #[inline(always)]
86    pub fn cpu_int_pri_iter(&self) -> impl Iterator<Item = &CPU_INT_PRI> {
87        self.cpu_int_pri.iter()
88    }
89    #[doc = "0x148 - register description"]
90    #[inline(always)]
91    pub const fn cpu_int_thresh(&self) -> &CPU_INT_THRESH {
92        &self.cpu_int_thresh
93    }
94    #[doc = "0x7fc - register description"]
95    #[inline(always)]
96    pub const fn interrupt_reg_date(&self) -> &INTERRUPT_REG_DATE {
97        &self.interrupt_reg_date
98    }
99}
100#[doc = "CORE_0_INTR_MAP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_map::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_intr_map::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_map`] module"]
101pub type CORE_0_INTR_MAP = crate::Reg<core_0_intr_map::CORE_0_INTR_MAP_SPEC>;
102#[doc = ""]
103pub mod core_0_intr_map;
104#[doc = "CORE_0_INTR_STATUS (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_status`] module"]
105pub type CORE_0_INTR_STATUS = crate::Reg<core_0_intr_status::CORE_0_INTR_STATUS_SPEC>;
106#[doc = "register description"]
107pub mod core_0_intr_status;
108#[doc = "CLOCK_GATE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
109pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
110#[doc = "register description"]
111pub mod clock_gate;
112#[doc = "CPU_INT_ENABLE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_int_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_int_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_enable`] module"]
113pub type CPU_INT_ENABLE = crate::Reg<cpu_int_enable::CPU_INT_ENABLE_SPEC>;
114#[doc = "register description"]
115pub mod cpu_int_enable;
116#[doc = "CPU_INT_TYPE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_int_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_int_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_type`] module"]
117pub type CPU_INT_TYPE = crate::Reg<cpu_int_type::CPU_INT_TYPE_SPEC>;
118#[doc = "register description"]
119pub mod cpu_int_type;
120#[doc = "CPU_INT_CLEAR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_int_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_int_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_clear`] module"]
121pub type CPU_INT_CLEAR = crate::Reg<cpu_int_clear::CPU_INT_CLEAR_SPEC>;
122#[doc = "register description"]
123pub mod cpu_int_clear;
124#[doc = "CPU_INT_EIP_STATUS (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_int_eip_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_eip_status`] module"]
125pub type CPU_INT_EIP_STATUS = crate::Reg<cpu_int_eip_status::CPU_INT_EIP_STATUS_SPEC>;
126#[doc = "register description"]
127pub mod cpu_int_eip_status;
128#[doc = "CPU_INT_PRI (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_int_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_int_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_pri`] module"]
129pub type CPU_INT_PRI = crate::Reg<cpu_int_pri::CPU_INT_PRI_SPEC>;
130#[doc = "register description"]
131pub mod cpu_int_pri;
132#[doc = "CPU_INT_THRESH (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_int_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_int_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_thresh`] module"]
133pub type CPU_INT_THRESH = crate::Reg<cpu_int_thresh::CPU_INT_THRESH_SPEC>;
134#[doc = "register description"]
135pub mod cpu_int_thresh;
136#[doc = "INTERRUPT_REG_DATE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_reg_date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_reg_date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_reg_date`] module"]
137pub type INTERRUPT_REG_DATE = crate::Reg<interrupt_reg_date::INTERRUPT_REG_DATE_SPEC>;
138#[doc = "register description"]
139pub mod interrupt_reg_date;
esp32c2/interrupt_core0.rs

esp32c2/
interrupt_core0.rs
