esp32c2/apb_saradc/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `START_FORCE` reader - Need add description"]
6pub type START_FORCE_R = crate::BitReader;
7#[doc = "Field `START_FORCE` writer - Need add description"]
8pub type START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `START` reader - Need add description"]
10pub type START_R = crate::BitReader;
11#[doc = "Field `START` writer - Need add description"]
12pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAR_CLK_GATED` reader - Need add description"]
14pub type SAR_CLK_GATED_R = crate::BitReader;
15#[doc = "Field `SAR_CLK_GATED` writer - Need add description"]
16pub type SAR_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR_CLK_DIV` reader - SAR clock divider"]
18pub type SAR_CLK_DIV_R = crate::FieldReader;
19#[doc = "Field `SAR_CLK_DIV` writer - SAR clock divider"]
20pub type SAR_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21#[doc = "Field `SAR_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
22pub type SAR_PATT_LEN_R = crate::FieldReader;
23#[doc = "Field `SAR_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
24pub type SAR_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `SAR_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC1 CTRL"]
26pub type SAR_PATT_P_CLEAR_R = crate::BitReader;
27#[doc = "Field `SAR_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC1 CTRL"]
28pub type SAR_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `XPD_SAR_FORCE` reader - force option to xpd sar blocks"]
30pub type XPD_SAR_FORCE_R = crate::FieldReader;
31#[doc = "Field `XPD_SAR_FORCE` writer - force option to xpd sar blocks"]
32pub type XPD_SAR_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `WAIT_ARB_CYCLE` reader - wait arbit signal stable after sar_done"]
34pub type WAIT_ARB_CYCLE_R = crate::FieldReader;
35#[doc = "Field `WAIT_ARB_CYCLE` writer - wait arbit signal stable after sar_done"]
36pub type WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37impl R {
38    #[doc = "Bit 0 - Need add description"]
39    #[inline(always)]
40    pub fn start_force(&self) -> START_FORCE_R {
41        START_FORCE_R::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Need add description"]
44    #[inline(always)]
45    pub fn start(&self) -> START_R {
46        START_R::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bit 6 - Need add description"]
49    #[inline(always)]
50    pub fn sar_clk_gated(&self) -> SAR_CLK_GATED_R {
51        SAR_CLK_GATED_R::new(((self.bits >> 6) & 1) != 0)
52    }
53    #[doc = "Bits 7:14 - SAR clock divider"]
54    #[inline(always)]
55    pub fn sar_clk_div(&self) -> SAR_CLK_DIV_R {
56        SAR_CLK_DIV_R::new(((self.bits >> 7) & 0xff) as u8)
57    }
58    #[doc = "Bits 15:17 - 0 ~ 15 means length 1 ~ 16"]
59    #[inline(always)]
60    pub fn sar_patt_len(&self) -> SAR_PATT_LEN_R {
61        SAR_PATT_LEN_R::new(((self.bits >> 15) & 7) as u8)
62    }
63    #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
64    #[inline(always)]
65    pub fn sar_patt_p_clear(&self) -> SAR_PATT_P_CLEAR_R {
66        SAR_PATT_P_CLEAR_R::new(((self.bits >> 23) & 1) != 0)
67    }
68    #[doc = "Bits 27:28 - force option to xpd sar blocks"]
69    #[inline(always)]
70    pub fn xpd_sar_force(&self) -> XPD_SAR_FORCE_R {
71        XPD_SAR_FORCE_R::new(((self.bits >> 27) & 3) as u8)
72    }
73    #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
74    #[inline(always)]
75    pub fn wait_arb_cycle(&self) -> WAIT_ARB_CYCLE_R {
76        WAIT_ARB_CYCLE_R::new(((self.bits >> 30) & 3) as u8)
77    }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82        f.debug_struct("CTRL")
83            .field("start_force", &self.start_force())
84            .field("start", &self.start())
85            .field("sar_clk_gated", &self.sar_clk_gated())
86            .field("sar_clk_div", &self.sar_clk_div())
87            .field("sar_patt_len", &self.sar_patt_len())
88            .field("sar_patt_p_clear", &self.sar_patt_p_clear())
89            .field("xpd_sar_force", &self.xpd_sar_force())
90            .field("wait_arb_cycle", &self.wait_arb_cycle())
91            .finish()
92    }
93}
94impl W {
95    #[doc = "Bit 0 - Need add description"]
96    #[inline(always)]
97    pub fn start_force(&mut self) -> START_FORCE_W<CTRL_SPEC> {
98        START_FORCE_W::new(self, 0)
99    }
100    #[doc = "Bit 1 - Need add description"]
101    #[inline(always)]
102    pub fn start(&mut self) -> START_W<CTRL_SPEC> {
103        START_W::new(self, 1)
104    }
105    #[doc = "Bit 6 - Need add description"]
106    #[inline(always)]
107    pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<CTRL_SPEC> {
108        SAR_CLK_GATED_W::new(self, 6)
109    }
110    #[doc = "Bits 7:14 - SAR clock divider"]
111    #[inline(always)]
112    pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<CTRL_SPEC> {
113        SAR_CLK_DIV_W::new(self, 7)
114    }
115    #[doc = "Bits 15:17 - 0 ~ 15 means length 1 ~ 16"]
116    #[inline(always)]
117    pub fn sar_patt_len(&mut self) -> SAR_PATT_LEN_W<CTRL_SPEC> {
118        SAR_PATT_LEN_W::new(self, 15)
119    }
120    #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
121    #[inline(always)]
122    pub fn sar_patt_p_clear(&mut self) -> SAR_PATT_P_CLEAR_W<CTRL_SPEC> {
123        SAR_PATT_P_CLEAR_W::new(self, 23)
124    }
125    #[doc = "Bits 27:28 - force option to xpd sar blocks"]
126    #[inline(always)]
127    pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<CTRL_SPEC> {
128        XPD_SAR_FORCE_W::new(self, 27)
129    }
130    #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
131    #[inline(always)]
132    pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<CTRL_SPEC> {
133        WAIT_ARB_CYCLE_W::new(self, 30)
134    }
135}
136#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct CTRL_SPEC;
138impl crate::RegisterSpec for CTRL_SPEC {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
142impl crate::Readable for CTRL_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
144impl crate::Writable for CTRL_SPEC {
145    type Safety = crate::Unsafe;
146}
147#[doc = "`reset()` method sets CTRL to value 0x4003_8240"]
148impl crate::Resettable for CTRL_SPEC {
149    const RESET_VALUE: u32 = 0x4003_8240;
150}
esp32c2/apb_saradc/ctrl.rs

esp32c2/apb_saradc/
ctrl.rs
