1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `RXFIFO_FULL` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
4pub type RXFIFO_FULL_R = crate::BitReader;
5#[doc = "Field `TXFIFO_EMPTY` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
6pub type TXFIFO_EMPTY_R = crate::BitReader;
7#[doc = "Field `PARITY_ERR` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
8pub type PARITY_ERR_R = crate::BitReader;
9#[doc = "Field `FRM_ERR` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."]
10pub type FRM_ERR_R = crate::BitReader;
11#[doc = "Field `RXFIFO_OVF` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
12pub type RXFIFO_OVF_R = crate::BitReader;
13#[doc = "Field `DSR_CHG` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
14pub type DSR_CHG_R = crate::BitReader;
15#[doc = "Field `CTS_CHG` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
16pub type CTS_CHG_R = crate::BitReader;
17#[doc = "Field `BRK_DET` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
18pub type BRK_DET_R = crate::BitReader;
19#[doc = "Field `RXFIFO_TOUT` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
20pub type RXFIFO_TOUT_R = crate::BitReader;
21#[doc = "Field `SW_XON` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
22pub type SW_XON_R = crate::BitReader;
23#[doc = "Field `SW_XOFF` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
24pub type SW_XOFF_R = crate::BitReader;
25#[doc = "Field `GLITCH_DET` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
26pub type GLITCH_DET_R = crate::BitReader;
27#[doc = "Field `TX_BRK_DONE` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
28pub type TX_BRK_DONE_R = crate::BitReader;
29#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
30pub type TX_BRK_IDLE_DONE_R = crate::BitReader;
31#[doc = "Field `TX_DONE` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
32pub type TX_DONE_R = crate::BitReader;
33#[doc = "Field `RS485_PARITY_ERR` reader - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1."]
34pub type RS485_PARITY_ERR_R = crate::BitReader;
35#[doc = "Field `RS485_FRM_ERR` reader - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1."]
36pub type RS485_FRM_ERR_R = crate::BitReader;
37#[doc = "Field `RS485_CLASH` reader - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1."]
38pub type RS485_CLASH_R = crate::BitReader;
39#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
40pub type AT_CMD_CHAR_DET_R = crate::BitReader;
41#[doc = "Field `WAKEUP` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."]
42pub type WAKEUP_R = crate::BitReader;
43impl R {
44 #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
45 #[inline(always)]
46 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
47 RXFIFO_FULL_R::new((self.bits & 1) != 0)
48 }
49 #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
50 #[inline(always)]
51 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
52 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
53 }
54 #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
55 #[inline(always)]
56 pub fn parity_err(&self) -> PARITY_ERR_R {
57 PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0)
58 }
59 #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."]
60 #[inline(always)]
61 pub fn frm_err(&self) -> FRM_ERR_R {
62 FRM_ERR_R::new(((self.bits >> 3) & 1) != 0)
63 }
64 #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
65 #[inline(always)]
66 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
67 RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0)
68 }
69 #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
70 #[inline(always)]
71 pub fn dsr_chg(&self) -> DSR_CHG_R {
72 DSR_CHG_R::new(((self.bits >> 5) & 1) != 0)
73 }
74 #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
75 #[inline(always)]
76 pub fn cts_chg(&self) -> CTS_CHG_R {
77 CTS_CHG_R::new(((self.bits >> 6) & 1) != 0)
78 }
79 #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
80 #[inline(always)]
81 pub fn brk_det(&self) -> BRK_DET_R {
82 BRK_DET_R::new(((self.bits >> 7) & 1) != 0)
83 }
84 #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
85 #[inline(always)]
86 pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R {
87 RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0)
88 }
89 #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
90 #[inline(always)]
91 pub fn sw_xon(&self) -> SW_XON_R {
92 SW_XON_R::new(((self.bits >> 9) & 1) != 0)
93 }
94 #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
95 #[inline(always)]
96 pub fn sw_xoff(&self) -> SW_XOFF_R {
97 SW_XOFF_R::new(((self.bits >> 10) & 1) != 0)
98 }
99 #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
100 #[inline(always)]
101 pub fn glitch_det(&self) -> GLITCH_DET_R {
102 GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0)
103 }
104 #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
105 #[inline(always)]
106 pub fn tx_brk_done(&self) -> TX_BRK_DONE_R {
107 TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0)
108 }
109 #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
110 #[inline(always)]
111 pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R {
112 TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0)
113 }
114 #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
115 #[inline(always)]
116 pub fn tx_done(&self) -> TX_DONE_R {
117 TX_DONE_R::new(((self.bits >> 14) & 1) != 0)
118 }
119 #[doc = "Bit 15 - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1."]
120 #[inline(always)]
121 pub fn rs485_parity_err(&self) -> RS485_PARITY_ERR_R {
122 RS485_PARITY_ERR_R::new(((self.bits >> 15) & 1) != 0)
123 }
124 #[doc = "Bit 16 - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1."]
125 #[inline(always)]
126 pub fn rs485_frm_err(&self) -> RS485_FRM_ERR_R {
127 RS485_FRM_ERR_R::new(((self.bits >> 16) & 1) != 0)
128 }
129 #[doc = "Bit 17 - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1."]
130 #[inline(always)]
131 pub fn rs485_clash(&self) -> RS485_CLASH_R {
132 RS485_CLASH_R::new(((self.bits >> 17) & 1) != 0)
133 }
134 #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
135 #[inline(always)]
136 pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R {
137 AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0)
138 }
139 #[doc = "Bit 19 - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."]
140 #[inline(always)]
141 pub fn wakeup(&self) -> WAKEUP_R {
142 WAKEUP_R::new(((self.bits >> 19) & 1) != 0)
143 }
144}
145#[cfg(feature = "impl-register-debug")]
146impl core::fmt::Debug for R {
147 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
148 f.debug_struct("INT_ST")
149 .field("rxfifo_full", &self.rxfifo_full())
150 .field("txfifo_empty", &self.txfifo_empty())
151 .field("parity_err", &self.parity_err())
152 .field("frm_err", &self.frm_err())
153 .field("rxfifo_ovf", &self.rxfifo_ovf())
154 .field("dsr_chg", &self.dsr_chg())
155 .field("cts_chg", &self.cts_chg())
156 .field("brk_det", &self.brk_det())
157 .field("rxfifo_tout", &self.rxfifo_tout())
158 .field("sw_xon", &self.sw_xon())
159 .field("sw_xoff", &self.sw_xoff())
160 .field("glitch_det", &self.glitch_det())
161 .field("tx_brk_done", &self.tx_brk_done())
162 .field("tx_brk_idle_done", &self.tx_brk_idle_done())
163 .field("tx_done", &self.tx_done())
164 .field("rs485_parity_err", &self.rs485_parity_err())
165 .field("rs485_frm_err", &self.rs485_frm_err())
166 .field("rs485_clash", &self.rs485_clash())
167 .field("at_cmd_char_det", &self.at_cmd_char_det())
168 .field("wakeup", &self.wakeup())
169 .finish()
170 }
171}
172#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
173pub struct INT_ST_SPEC;
174impl crate::RegisterSpec for INT_ST_SPEC {
175 type Ux = u32;
176}
177#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
178impl crate::Readable for INT_ST_SPEC {}
179#[doc = "`reset()` method sets INT_ST to value 0"]
180impl crate::Resettable for INT_ST_SPEC {
181 const RESET_VALUE: u32 = 0;
182}