esp32c2/systimer/
unit_load.rs

1#[doc = "Register `UNIT%s_LOAD` writer"]
2pub type W = crate::W<UNIT_LOAD_SPEC>;
3#[doc = "Field `LOAD` writer - timer unit0 sync enable signal"]
4pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for crate::generic::Reg<UNIT_LOAD_SPEC> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bit 0 - timer unit0 sync enable signal"]
13    #[inline(always)]
14    pub fn load(&mut self) -> LOAD_W<UNIT_LOAD_SPEC> {
15        LOAD_W::new(self, 0)
16    }
17}
18#[doc = "system timer unit%s conf sync register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`unit_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct UNIT_LOAD_SPEC;
20impl crate::RegisterSpec for UNIT_LOAD_SPEC {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`unit_load::W`](W) writer structure"]
24impl crate::Writable for UNIT_LOAD_SPEC {
25    type Safety = crate::Unsafe;
26    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
27    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
28}
29#[doc = "`reset()` method sets UNIT%s_LOAD to value 0"]
30impl crate::Resettable for UNIT_LOAD_SPEC {
31    const RESET_VALUE: u32 = 0;
32}
esp32c2/systimer/unit_load.rs

esp32c2/systimer/
unit_load.rs
