esp32c2/systimer/
int_clr.rs1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TARGET(0-2)` writer - interupt%s clear"]
4pub type TARGET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
7 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8 write!(f, "(not readable)")
9 }
10}
11impl W {
12 #[doc = "interupt(0-2) clear"]
13 #[doc = ""]
14 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
15 #[inline(always)]
16 pub fn target(&mut self, n: u8) -> TARGET_W<INT_CLR_SPEC> {
17 #[allow(clippy::no_effect)]
18 [(); 3][n as usize];
19 TARGET_W::new(self, n)
20 }
21 #[doc = "Bit 0 - interupt0 clear"]
22 #[inline(always)]
23 pub fn target0(&mut self) -> TARGET_W<INT_CLR_SPEC> {
24 TARGET_W::new(self, 0)
25 }
26 #[doc = "Bit 1 - interupt1 clear"]
27 #[inline(always)]
28 pub fn target1(&mut self) -> TARGET_W<INT_CLR_SPEC> {
29 TARGET_W::new(self, 1)
30 }
31 #[doc = "Bit 2 - interupt2 clear"]
32 #[inline(always)]
33 pub fn target2(&mut self) -> TARGET_W<INT_CLR_SPEC> {
34 TARGET_W::new(self, 2)
35 }
36}
37#[doc = "systimer interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
38pub struct INT_CLR_SPEC;
39impl crate::RegisterSpec for INT_CLR_SPEC {
40 type Ux = u32;
41}
42#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
43impl crate::Writable for INT_CLR_SPEC {
44 type Safety = crate::Unsafe;
45 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
46 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07;
47}
48#[doc = "`reset()` method sets INT_CLR to value 0"]
49impl crate::Resettable for INT_CLR_SPEC {
50 const RESET_VALUE: u32 = 0;
51}