esp32c2/spi2/
dma_int_clr.rs1#[doc = "Register `DMA_INT_CLR` writer"]
2pub type W = crate::W<DMA_INT_CLR_SPEC>;
3#[doc = "Field `DMA_INFIFO_FULL_ERR` writer - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
4pub type DMA_INFIFO_FULL_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `DMA_OUTFIFO_EMPTY_ERR` writer - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
6pub type DMA_OUTFIFO_EMPTY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `SLV_EX_QPI` writer - The clear bit for SPI slave Ex_QPI interrupt."]
8pub type SLV_EX_QPI_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SLV_EN_QPI` writer - The clear bit for SPI slave En_QPI interrupt."]
10pub type SLV_EN_QPI_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `SLV_CMD7` writer - The clear bit for SPI slave CMD7 interrupt."]
12pub type SLV_CMD7_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `SLV_CMD8` writer - The clear bit for SPI slave CMD8 interrupt."]
14pub type SLV_CMD8_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `SLV_CMD9` writer - The clear bit for SPI slave CMD9 interrupt."]
16pub type SLV_CMD9_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `SLV_CMDA` writer - The clear bit for SPI slave CMDA interrupt."]
18pub type SLV_CMDA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `SLV_RD_DMA_DONE` writer - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
20pub type SLV_RD_DMA_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `SLV_WR_DMA_DONE` writer - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
22pub type SLV_WR_DMA_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `SLV_RD_BUF_DONE` writer - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
24pub type SLV_RD_BUF_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `SLV_WR_BUF_DONE` writer - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
26pub type SLV_WR_BUF_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TRANS_DONE` writer - The clear bit for SPI_TRANS_DONE_INT interrupt."]
28pub type TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `DMA_SEG_TRANS_DONE` writer - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
30pub type DMA_SEG_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SEG_MAGIC_ERR` writer - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
32pub type SEG_MAGIC_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SLV_BUF_ADDR_ERR` writer - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
34pub type SLV_BUF_ADDR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `SLV_CMD_ERR` writer - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."]
36pub type SLV_CMD_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `MST_RX_AFIFO_WFULL_ERR` writer - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
38pub type MST_RX_AFIFO_WFULL_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `MST_TX_AFIFO_REMPTY_ERR` writer - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
40pub type MST_TX_AFIFO_REMPTY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `APP2` writer - The clear bit for SPI_APP2_INT interrupt."]
42pub type APP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[doc = "Field `APP1` writer - The clear bit for SPI_APP1_INT interrupt."]
44pub type APP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for crate::generic::Reg<DMA_INT_CLR_SPEC> {
47 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
48 write!(f, "(not readable)")
49 }
50}
51impl W {
52 #[doc = "Bit 0 - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
53 #[inline(always)]
54 pub fn dma_infifo_full_err(&mut self) -> DMA_INFIFO_FULL_ERR_W<DMA_INT_CLR_SPEC> {
55 DMA_INFIFO_FULL_ERR_W::new(self, 0)
56 }
57 #[doc = "Bit 1 - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
58 #[inline(always)]
59 pub fn dma_outfifo_empty_err(&mut self) -> DMA_OUTFIFO_EMPTY_ERR_W<DMA_INT_CLR_SPEC> {
60 DMA_OUTFIFO_EMPTY_ERR_W::new(self, 1)
61 }
62 #[doc = "Bit 2 - The clear bit for SPI slave Ex_QPI interrupt."]
63 #[inline(always)]
64 pub fn slv_ex_qpi(&mut self) -> SLV_EX_QPI_W<DMA_INT_CLR_SPEC> {
65 SLV_EX_QPI_W::new(self, 2)
66 }
67 #[doc = "Bit 3 - The clear bit for SPI slave En_QPI interrupt."]
68 #[inline(always)]
69 pub fn slv_en_qpi(&mut self) -> SLV_EN_QPI_W<DMA_INT_CLR_SPEC> {
70 SLV_EN_QPI_W::new(self, 3)
71 }
72 #[doc = "Bit 4 - The clear bit for SPI slave CMD7 interrupt."]
73 #[inline(always)]
74 pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_CLR_SPEC> {
75 SLV_CMD7_W::new(self, 4)
76 }
77 #[doc = "Bit 5 - The clear bit for SPI slave CMD8 interrupt."]
78 #[inline(always)]
79 pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_CLR_SPEC> {
80 SLV_CMD8_W::new(self, 5)
81 }
82 #[doc = "Bit 6 - The clear bit for SPI slave CMD9 interrupt."]
83 #[inline(always)]
84 pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_CLR_SPEC> {
85 SLV_CMD9_W::new(self, 6)
86 }
87 #[doc = "Bit 7 - The clear bit for SPI slave CMDA interrupt."]
88 #[inline(always)]
89 pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_CLR_SPEC> {
90 SLV_CMDA_W::new(self, 7)
91 }
92 #[doc = "Bit 8 - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
93 #[inline(always)]
94 pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<DMA_INT_CLR_SPEC> {
95 SLV_RD_DMA_DONE_W::new(self, 8)
96 }
97 #[doc = "Bit 9 - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
98 #[inline(always)]
99 pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<DMA_INT_CLR_SPEC> {
100 SLV_WR_DMA_DONE_W::new(self, 9)
101 }
102 #[doc = "Bit 10 - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
103 #[inline(always)]
104 pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<DMA_INT_CLR_SPEC> {
105 SLV_RD_BUF_DONE_W::new(self, 10)
106 }
107 #[doc = "Bit 11 - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
108 #[inline(always)]
109 pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<DMA_INT_CLR_SPEC> {
110 SLV_WR_BUF_DONE_W::new(self, 11)
111 }
112 #[doc = "Bit 12 - The clear bit for SPI_TRANS_DONE_INT interrupt."]
113 #[inline(always)]
114 pub fn trans_done(&mut self) -> TRANS_DONE_W<DMA_INT_CLR_SPEC> {
115 TRANS_DONE_W::new(self, 12)
116 }
117 #[doc = "Bit 13 - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
118 #[inline(always)]
119 pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<DMA_INT_CLR_SPEC> {
120 DMA_SEG_TRANS_DONE_W::new(self, 13)
121 }
122 #[doc = "Bit 14 - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
123 #[inline(always)]
124 pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<DMA_INT_CLR_SPEC> {
125 SEG_MAGIC_ERR_W::new(self, 14)
126 }
127 #[doc = "Bit 15 - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
128 #[inline(always)]
129 pub fn slv_buf_addr_err(&mut self) -> SLV_BUF_ADDR_ERR_W<DMA_INT_CLR_SPEC> {
130 SLV_BUF_ADDR_ERR_W::new(self, 15)
131 }
132 #[doc = "Bit 16 - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."]
133 #[inline(always)]
134 pub fn slv_cmd_err(&mut self) -> SLV_CMD_ERR_W<DMA_INT_CLR_SPEC> {
135 SLV_CMD_ERR_W::new(self, 16)
136 }
137 #[doc = "Bit 17 - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
138 #[inline(always)]
139 pub fn mst_rx_afifo_wfull_err(&mut self) -> MST_RX_AFIFO_WFULL_ERR_W<DMA_INT_CLR_SPEC> {
140 MST_RX_AFIFO_WFULL_ERR_W::new(self, 17)
141 }
142 #[doc = "Bit 18 - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
143 #[inline(always)]
144 pub fn mst_tx_afifo_rempty_err(&mut self) -> MST_TX_AFIFO_REMPTY_ERR_W<DMA_INT_CLR_SPEC> {
145 MST_TX_AFIFO_REMPTY_ERR_W::new(self, 18)
146 }
147 #[doc = "Bit 19 - The clear bit for SPI_APP2_INT interrupt."]
148 #[inline(always)]
149 pub fn app2(&mut self) -> APP2_W<DMA_INT_CLR_SPEC> {
150 APP2_W::new(self, 19)
151 }
152 #[doc = "Bit 20 - The clear bit for SPI_APP1_INT interrupt."]
153 #[inline(always)]
154 pub fn app1(&mut self) -> APP1_W<DMA_INT_CLR_SPEC> {
155 APP1_W::new(self, 20)
156 }
157}
158#[doc = "SPI interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
159pub struct DMA_INT_CLR_SPEC;
160impl crate::RegisterSpec for DMA_INT_CLR_SPEC {
161 type Ux = u32;
162}
163#[doc = "`write(|w| ..)` method takes [`dma_int_clr::W`](W) writer structure"]
164impl crate::Writable for DMA_INT_CLR_SPEC {
165 type Safety = crate::Unsafe;
166 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
167 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_ffff;
168}
169#[doc = "`reset()` method sets DMA_INT_CLR to value 0"]
170impl crate::Resettable for DMA_INT_CLR_SPEC {
171 const RESET_VALUE: u32 = 0;
172}