esp32c2/spi2/
din_num.rs

1#[doc = "Register `DIN_NUM` reader"]
2pub type R = crate::R<DIN_NUM_SPEC>;
3#[doc = "Field `DIN0_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
4pub type DIN0_NUM_R = crate::FieldReader;
5#[doc = "Field `DIN1_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
6pub type DIN1_NUM_R = crate::FieldReader;
7#[doc = "Field `DIN2_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
8pub type DIN2_NUM_R = crate::FieldReader;
9#[doc = "Field `DIN3_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
10pub type DIN3_NUM_R = crate::FieldReader;
11#[doc = "Field `DIN4_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
12pub type DIN4_NUM_R = crate::FieldReader;
13#[doc = "Field `DIN5_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
14pub type DIN5_NUM_R = crate::FieldReader;
15#[doc = "Field `DIN6_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
16pub type DIN6_NUM_R = crate::FieldReader;
17#[doc = "Field `DIN7_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
18pub type DIN7_NUM_R = crate::FieldReader;
19impl R {
20    #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
21    #[inline(always)]
22    pub fn din0_num(&self) -> DIN0_NUM_R {
23        DIN0_NUM_R::new((self.bits & 3) as u8)
24    }
25    #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
26    #[inline(always)]
27    pub fn din1_num(&self) -> DIN1_NUM_R {
28        DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8)
29    }
30    #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
31    #[inline(always)]
32    pub fn din2_num(&self) -> DIN2_NUM_R {
33        DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8)
34    }
35    #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
36    #[inline(always)]
37    pub fn din3_num(&self) -> DIN3_NUM_R {
38        DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8)
39    }
40    #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
41    #[inline(always)]
42    pub fn din4_num(&self) -> DIN4_NUM_R {
43        DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8)
44    }
45    #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
46    #[inline(always)]
47    pub fn din5_num(&self) -> DIN5_NUM_R {
48        DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8)
49    }
50    #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
51    #[inline(always)]
52    pub fn din6_num(&self) -> DIN6_NUM_R {
53        DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8)
54    }
55    #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
56    #[inline(always)]
57    pub fn din7_num(&self) -> DIN7_NUM_R {
58        DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("DIN_NUM")
65            .field("din0_num", &self.din0_num())
66            .field("din1_num", &self.din1_num())
67            .field("din2_num", &self.din2_num())
68            .field("din3_num", &self.din3_num())
69            .field("din4_num", &self.din4_num())
70            .field("din5_num", &self.din5_num())
71            .field("din6_num", &self.din6_num())
72            .field("din7_num", &self.din7_num())
73            .finish()
74    }
75}
76#[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`din_num::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct DIN_NUM_SPEC;
78impl crate::RegisterSpec for DIN_NUM_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`din_num::R`](R) reader structure"]
82impl crate::Readable for DIN_NUM_SPEC {}
83#[doc = "`reset()` method sets DIN_NUM to value 0"]
84impl crate::Resettable for DIN_NUM_SPEC {
85    const RESET_VALUE: u32 = 0;
86}
esp32c2/spi2/din_num.rs

esp32c2/spi2/
din_num.rs
