1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Register `CMD` writer"]
4pub type W = crate::W<CMD_SPEC>;
5#[doc = "Field `SPI1_MST_ST` reader - The current status of SPI1 master FSM."]
6pub type SPI1_MST_ST_R = crate::FieldReader;
7#[doc = "Field `MSPI_ST` reader - The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."]
8pub type MSPI_ST_R = crate::FieldReader;
9#[doc = "Field `FLASH_PE` reader - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
10pub type FLASH_PE_R = crate::BitReader;
11#[doc = "Field `FLASH_PE` writer - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
12pub type FLASH_PE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
14pub type USR_R = crate::BitReader;
15#[doc = "Field `USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
16pub type USR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_HPM` reader - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
18pub type FLASH_HPM_R = crate::BitReader;
19#[doc = "Field `FLASH_HPM` writer - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
20pub type FLASH_HPM_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FLASH_RES` reader - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
22pub type FLASH_RES_R = crate::BitReader;
23#[doc = "Field `FLASH_RES` writer - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
24pub type FLASH_RES_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FLASH_DP` reader - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
26pub type FLASH_DP_R = crate::BitReader;
27#[doc = "Field `FLASH_DP` writer - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
28pub type FLASH_DP_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FLASH_CE` reader - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
30pub type FLASH_CE_R = crate::BitReader;
31#[doc = "Field `FLASH_CE` writer - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
32pub type FLASH_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FLASH_BE` reader - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
34pub type FLASH_BE_R = crate::BitReader;
35#[doc = "Field `FLASH_BE` writer - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
36pub type FLASH_BE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FLASH_SE` reader - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
38pub type FLASH_SE_R = crate::BitReader;
39#[doc = "Field `FLASH_SE` writer - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
40pub type FLASH_SE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FLASH_PP` reader - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
42pub type FLASH_PP_R = crate::BitReader;
43#[doc = "Field `FLASH_PP` writer - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
44pub type FLASH_PP_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FLASH_WRSR` reader - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
46pub type FLASH_WRSR_R = crate::BitReader;
47#[doc = "Field `FLASH_WRSR` writer - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
48pub type FLASH_WRSR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FLASH_RDSR` reader - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
50pub type FLASH_RDSR_R = crate::BitReader;
51#[doc = "Field `FLASH_RDSR` writer - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
52pub type FLASH_RDSR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `FLASH_RDID` reader - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
54pub type FLASH_RDID_R = crate::BitReader;
55#[doc = "Field `FLASH_RDID` writer - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
56pub type FLASH_RDID_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `FLASH_WRDI` reader - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
58pub type FLASH_WRDI_R = crate::BitReader;
59#[doc = "Field `FLASH_WRDI` writer - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
60pub type FLASH_WRDI_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FLASH_WREN` reader - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
62pub type FLASH_WREN_R = crate::BitReader;
63#[doc = "Field `FLASH_WREN` writer - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
64pub type FLASH_WREN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `FLASH_READ` reader - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
66pub type FLASH_READ_R = crate::BitReader;
67#[doc = "Field `FLASH_READ` writer - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
68pub type FLASH_READ_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70 #[doc = "Bits 0:3 - The current status of SPI1 master FSM."]
71 #[inline(always)]
72 pub fn spi1_mst_st(&self) -> SPI1_MST_ST_R {
73 SPI1_MST_ST_R::new((self.bits & 0x0f) as u8)
74 }
75 #[doc = "Bits 4:7 - The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."]
76 #[inline(always)]
77 pub fn mspi_st(&self) -> MSPI_ST_R {
78 MSPI_ST_R::new(((self.bits >> 4) & 0x0f) as u8)
79 }
80 #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
81 #[inline(always)]
82 pub fn flash_pe(&self) -> FLASH_PE_R {
83 FLASH_PE_R::new(((self.bits >> 17) & 1) != 0)
84 }
85 #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
86 #[inline(always)]
87 pub fn usr(&self) -> USR_R {
88 USR_R::new(((self.bits >> 18) & 1) != 0)
89 }
90 #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
91 #[inline(always)]
92 pub fn flash_hpm(&self) -> FLASH_HPM_R {
93 FLASH_HPM_R::new(((self.bits >> 19) & 1) != 0)
94 }
95 #[doc = "Bit 20 - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
96 #[inline(always)]
97 pub fn flash_res(&self) -> FLASH_RES_R {
98 FLASH_RES_R::new(((self.bits >> 20) & 1) != 0)
99 }
100 #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
101 #[inline(always)]
102 pub fn flash_dp(&self) -> FLASH_DP_R {
103 FLASH_DP_R::new(((self.bits >> 21) & 1) != 0)
104 }
105 #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
106 #[inline(always)]
107 pub fn flash_ce(&self) -> FLASH_CE_R {
108 FLASH_CE_R::new(((self.bits >> 22) & 1) != 0)
109 }
110 #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
111 #[inline(always)]
112 pub fn flash_be(&self) -> FLASH_BE_R {
113 FLASH_BE_R::new(((self.bits >> 23) & 1) != 0)
114 }
115 #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
116 #[inline(always)]
117 pub fn flash_se(&self) -> FLASH_SE_R {
118 FLASH_SE_R::new(((self.bits >> 24) & 1) != 0)
119 }
120 #[doc = "Bit 25 - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
121 #[inline(always)]
122 pub fn flash_pp(&self) -> FLASH_PP_R {
123 FLASH_PP_R::new(((self.bits >> 25) & 1) != 0)
124 }
125 #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
126 #[inline(always)]
127 pub fn flash_wrsr(&self) -> FLASH_WRSR_R {
128 FLASH_WRSR_R::new(((self.bits >> 26) & 1) != 0)
129 }
130 #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
131 #[inline(always)]
132 pub fn flash_rdsr(&self) -> FLASH_RDSR_R {
133 FLASH_RDSR_R::new(((self.bits >> 27) & 1) != 0)
134 }
135 #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
136 #[inline(always)]
137 pub fn flash_rdid(&self) -> FLASH_RDID_R {
138 FLASH_RDID_R::new(((self.bits >> 28) & 1) != 0)
139 }
140 #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
141 #[inline(always)]
142 pub fn flash_wrdi(&self) -> FLASH_WRDI_R {
143 FLASH_WRDI_R::new(((self.bits >> 29) & 1) != 0)
144 }
145 #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
146 #[inline(always)]
147 pub fn flash_wren(&self) -> FLASH_WREN_R {
148 FLASH_WREN_R::new(((self.bits >> 30) & 1) != 0)
149 }
150 #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
151 #[inline(always)]
152 pub fn flash_read(&self) -> FLASH_READ_R {
153 FLASH_READ_R::new(((self.bits >> 31) & 1) != 0)
154 }
155}
156#[cfg(feature = "impl-register-debug")]
157impl core::fmt::Debug for R {
158 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
159 f.debug_struct("CMD")
160 .field("spi1_mst_st", &self.spi1_mst_st())
161 .field("mspi_st", &self.mspi_st())
162 .field("flash_pe", &self.flash_pe())
163 .field("usr", &self.usr())
164 .field("flash_hpm", &self.flash_hpm())
165 .field("flash_res", &self.flash_res())
166 .field("flash_dp", &self.flash_dp())
167 .field("flash_ce", &self.flash_ce())
168 .field("flash_be", &self.flash_be())
169 .field("flash_se", &self.flash_se())
170 .field("flash_pp", &self.flash_pp())
171 .field("flash_wrsr", &self.flash_wrsr())
172 .field("flash_rdsr", &self.flash_rdsr())
173 .field("flash_rdid", &self.flash_rdid())
174 .field("flash_wrdi", &self.flash_wrdi())
175 .field("flash_wren", &self.flash_wren())
176 .field("flash_read", &self.flash_read())
177 .finish()
178 }
179}
180impl W {
181 #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
182 #[inline(always)]
183 pub fn flash_pe(&mut self) -> FLASH_PE_W<CMD_SPEC> {
184 FLASH_PE_W::new(self, 17)
185 }
186 #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
187 #[inline(always)]
188 pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
189 USR_W::new(self, 18)
190 }
191 #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
192 #[inline(always)]
193 pub fn flash_hpm(&mut self) -> FLASH_HPM_W<CMD_SPEC> {
194 FLASH_HPM_W::new(self, 19)
195 }
196 #[doc = "Bit 20 - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
197 #[inline(always)]
198 pub fn flash_res(&mut self) -> FLASH_RES_W<CMD_SPEC> {
199 FLASH_RES_W::new(self, 20)
200 }
201 #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
202 #[inline(always)]
203 pub fn flash_dp(&mut self) -> FLASH_DP_W<CMD_SPEC> {
204 FLASH_DP_W::new(self, 21)
205 }
206 #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
207 #[inline(always)]
208 pub fn flash_ce(&mut self) -> FLASH_CE_W<CMD_SPEC> {
209 FLASH_CE_W::new(self, 22)
210 }
211 #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
212 #[inline(always)]
213 pub fn flash_be(&mut self) -> FLASH_BE_W<CMD_SPEC> {
214 FLASH_BE_W::new(self, 23)
215 }
216 #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
217 #[inline(always)]
218 pub fn flash_se(&mut self) -> FLASH_SE_W<CMD_SPEC> {
219 FLASH_SE_W::new(self, 24)
220 }
221 #[doc = "Bit 25 - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
222 #[inline(always)]
223 pub fn flash_pp(&mut self) -> FLASH_PP_W<CMD_SPEC> {
224 FLASH_PP_W::new(self, 25)
225 }
226 #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
227 #[inline(always)]
228 pub fn flash_wrsr(&mut self) -> FLASH_WRSR_W<CMD_SPEC> {
229 FLASH_WRSR_W::new(self, 26)
230 }
231 #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
232 #[inline(always)]
233 pub fn flash_rdsr(&mut self) -> FLASH_RDSR_W<CMD_SPEC> {
234 FLASH_RDSR_W::new(self, 27)
235 }
236 #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
237 #[inline(always)]
238 pub fn flash_rdid(&mut self) -> FLASH_RDID_W<CMD_SPEC> {
239 FLASH_RDID_W::new(self, 28)
240 }
241 #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
242 #[inline(always)]
243 pub fn flash_wrdi(&mut self) -> FLASH_WRDI_W<CMD_SPEC> {
244 FLASH_WRDI_W::new(self, 29)
245 }
246 #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
247 #[inline(always)]
248 pub fn flash_wren(&mut self) -> FLASH_WREN_W<CMD_SPEC> {
249 FLASH_WREN_W::new(self, 30)
250 }
251 #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
252 #[inline(always)]
253 pub fn flash_read(&mut self) -> FLASH_READ_W<CMD_SPEC> {
254 FLASH_READ_W::new(self, 31)
255 }
256}
257#[doc = "SPI1 memory command register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
258pub struct CMD_SPEC;
259impl crate::RegisterSpec for CMD_SPEC {
260 type Ux = u32;
261}
262#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
263impl crate::Readable for CMD_SPEC {}
264#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
265impl crate::Writable for CMD_SPEC {
266 type Safety = crate::Unsafe;
267 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
268 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
269}
270#[doc = "`reset()` method sets CMD to value 0"]
271impl crate::Resettable for CMD_SPEC {
272 const RESET_VALUE: u32 = 0;
273}