1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 cmd: CMD,
6 addr: ADDR,
7 ctrl: CTRL,
8 ctrl1: CTRL1,
9 ctrl2: CTRL2,
10 clock: CLOCK,
11 user: USER,
12 user1: USER1,
13 user2: USER2,
14 mosi_dlen: MOSI_DLEN,
15 miso_dlen: MISO_DLEN,
16 rd_status: RD_STATUS,
17 _reserved12: [u8; 0x04],
18 misc: MISC,
19 tx_crc: TX_CRC,
20 cache_fctrl: CACHE_FCTRL,
21 _reserved15: [u8; 0x18],
22 w: [W; 16],
23 flash_waiti_ctrl: FLASH_WAITI_CTRL,
24 flash_sus_ctrl: FLASH_SUS_CTRL,
25 flash_sus_cmd: FLASH_SUS_CMD,
26 sus_status: SUS_STATUS,
27 timing_cali: TIMING_CALI,
28 _reserved21: [u8; 0x14],
29 int_ena: INT_ENA,
30 int_clr: INT_CLR,
31 int_raw: INT_RAW,
32 int_st: INT_ST,
33 _reserved25: [u8; 0x0c],
34 clock_gate: CLOCK_GATE,
35 _reserved26: [u8; 0x031c],
36 date: DATE,
37}
38impl RegisterBlock {
39 #[doc = "0x00 - SPI1 memory command register"]
40 #[inline(always)]
41 pub const fn cmd(&self) -> &CMD {
42 &self.cmd
43 }
44 #[doc = "0x04 - SPI1 address register"]
45 #[inline(always)]
46 pub const fn addr(&self) -> &ADDR {
47 &self.addr
48 }
49 #[doc = "0x08 - SPI1 control register."]
50 #[inline(always)]
51 pub const fn ctrl(&self) -> &CTRL {
52 &self.ctrl
53 }
54 #[doc = "0x0c - SPI1 control1 register."]
55 #[inline(always)]
56 pub const fn ctrl1(&self) -> &CTRL1 {
57 &self.ctrl1
58 }
59 #[doc = "0x10 - SPI1 control2 register."]
60 #[inline(always)]
61 pub const fn ctrl2(&self) -> &CTRL2 {
62 &self.ctrl2
63 }
64 #[doc = "0x14 - SPI1 clock division control register."]
65 #[inline(always)]
66 pub const fn clock(&self) -> &CLOCK {
67 &self.clock
68 }
69 #[doc = "0x18 - SPI1 user register."]
70 #[inline(always)]
71 pub const fn user(&self) -> &USER {
72 &self.user
73 }
74 #[doc = "0x1c - SPI1 user1 register."]
75 #[inline(always)]
76 pub const fn user1(&self) -> &USER1 {
77 &self.user1
78 }
79 #[doc = "0x20 - SPI1 user2 register."]
80 #[inline(always)]
81 pub const fn user2(&self) -> &USER2 {
82 &self.user2
83 }
84 #[doc = "0x24 - SPI1 send data bit length control register."]
85 #[inline(always)]
86 pub const fn mosi_dlen(&self) -> &MOSI_DLEN {
87 &self.mosi_dlen
88 }
89 #[doc = "0x28 - SPI1 receive data bit length control register."]
90 #[inline(always)]
91 pub const fn miso_dlen(&self) -> &MISO_DLEN {
92 &self.miso_dlen
93 }
94 #[doc = "0x2c - SPI1 status register."]
95 #[inline(always)]
96 pub const fn rd_status(&self) -> &RD_STATUS {
97 &self.rd_status
98 }
99 #[doc = "0x34 - SPI1 misc register"]
100 #[inline(always)]
101 pub const fn misc(&self) -> &MISC {
102 &self.misc
103 }
104 #[doc = "0x38 - SPI1 TX CRC data register."]
105 #[inline(always)]
106 pub const fn tx_crc(&self) -> &TX_CRC {
107 &self.tx_crc
108 }
109 #[doc = "0x3c - SPI1 bit mode control register."]
110 #[inline(always)]
111 pub const fn cache_fctrl(&self) -> &CACHE_FCTRL {
112 &self.cache_fctrl
113 }
114 #[doc = "0x58..0x98 - SPI1 memory data buffer%s"]
115 #[inline(always)]
116 pub const fn w(&self, n: usize) -> &W {
117 &self.w[n]
118 }
119 #[doc = "Iterator for array of:"]
120 #[doc = "0x58..0x98 - SPI1 memory data buffer%s"]
121 #[inline(always)]
122 pub fn w_iter(&self) -> impl Iterator<Item = &W> {
123 self.w.iter()
124 }
125 #[doc = "0x98 - SPI1 wait idle control register"]
126 #[inline(always)]
127 pub const fn flash_waiti_ctrl(&self) -> &FLASH_WAITI_CTRL {
128 &self.flash_waiti_ctrl
129 }
130 #[doc = "0x9c - SPI1 flash suspend control register"]
131 #[inline(always)]
132 pub const fn flash_sus_ctrl(&self) -> &FLASH_SUS_CTRL {
133 &self.flash_sus_ctrl
134 }
135 #[doc = "0xa0 - SPI1 flash suspend command register"]
136 #[inline(always)]
137 pub const fn flash_sus_cmd(&self) -> &FLASH_SUS_CMD {
138 &self.flash_sus_cmd
139 }
140 #[doc = "0xa4 - SPI1 flash suspend status register"]
141 #[inline(always)]
142 pub const fn sus_status(&self) -> &SUS_STATUS {
143 &self.sus_status
144 }
145 #[doc = "0xa8 - SPI1 timing control register"]
146 #[inline(always)]
147 pub const fn timing_cali(&self) -> &TIMING_CALI {
148 &self.timing_cali
149 }
150 #[doc = "0xc0 - SPI1 interrupt enable register"]
151 #[inline(always)]
152 pub const fn int_ena(&self) -> &INT_ENA {
153 &self.int_ena
154 }
155 #[doc = "0xc4 - SPI1 interrupt clear register"]
156 #[inline(always)]
157 pub const fn int_clr(&self) -> &INT_CLR {
158 &self.int_clr
159 }
160 #[doc = "0xc8 - SPI1 interrupt raw register"]
161 #[inline(always)]
162 pub const fn int_raw(&self) -> &INT_RAW {
163 &self.int_raw
164 }
165 #[doc = "0xcc - SPI1 interrupt status register"]
166 #[inline(always)]
167 pub const fn int_st(&self) -> &INT_ST {
168 &self.int_st
169 }
170 #[doc = "0xdc - SPI1 clk_gate register"]
171 #[inline(always)]
172 pub const fn clock_gate(&self) -> &CLOCK_GATE {
173 &self.clock_gate
174 }
175 #[doc = "0x3fc - Version control register"]
176 #[inline(always)]
177 pub const fn date(&self) -> &DATE {
178 &self.date
179 }
180}
181#[doc = "CMD (rw) register accessor: SPI1 memory command register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"]
182pub type CMD = crate::Reg<cmd::CMD_SPEC>;
183#[doc = "SPI1 memory command register"]
184pub mod cmd;
185#[doc = "ADDR (rw) register accessor: SPI1 address register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`] module"]
186pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
187#[doc = "SPI1 address register"]
188pub mod addr;
189#[doc = "CTRL (rw) register accessor: SPI1 control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
190pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
191#[doc = "SPI1 control register."]
192pub mod ctrl;
193#[doc = "CTRL1 (rw) register accessor: SPI1 control1 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"]
194pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
195#[doc = "SPI1 control1 register."]
196pub mod ctrl1;
197#[doc = "CTRL2 (w) register accessor: SPI1 control2 register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"]
198pub type CTRL2 = crate::Reg<ctrl2::CTRL2_SPEC>;
199#[doc = "SPI1 control2 register."]
200pub mod ctrl2;
201#[doc = "CLOCK (rw) register accessor: SPI1 clock division control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock`] module"]
202pub type CLOCK = crate::Reg<clock::CLOCK_SPEC>;
203#[doc = "SPI1 clock division control register."]
204pub mod clock;
205#[doc = "USER (rw) register accessor: SPI1 user register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user`] module"]
206pub type USER = crate::Reg<user::USER_SPEC>;
207#[doc = "SPI1 user register."]
208pub mod user;
209#[doc = "USER1 (rw) register accessor: SPI1 user1 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user1`] module"]
210pub type USER1 = crate::Reg<user1::USER1_SPEC>;
211#[doc = "SPI1 user1 register."]
212pub mod user1;
213#[doc = "USER2 (rw) register accessor: SPI1 user2 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user2`] module"]
214pub type USER2 = crate::Reg<user2::USER2_SPEC>;
215#[doc = "SPI1 user2 register."]
216pub mod user2;
217#[doc = "MOSI_DLEN (rw) register accessor: SPI1 send data bit length control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mosi_dlen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mosi_dlen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mosi_dlen`] module"]
218pub type MOSI_DLEN = crate::Reg<mosi_dlen::MOSI_DLEN_SPEC>;
219#[doc = "SPI1 send data bit length control register."]
220pub mod mosi_dlen;
221#[doc = "MISO_DLEN (rw) register accessor: SPI1 receive data bit length control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`miso_dlen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`miso_dlen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miso_dlen`] module"]
222pub type MISO_DLEN = crate::Reg<miso_dlen::MISO_DLEN_SPEC>;
223#[doc = "SPI1 receive data bit length control register."]
224pub mod miso_dlen;
225#[doc = "RD_STATUS (rw) register accessor: SPI1 status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`rd_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rd_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_status`] module"]
226pub type RD_STATUS = crate::Reg<rd_status::RD_STATUS_SPEC>;
227#[doc = "SPI1 status register."]
228pub mod rd_status;
229#[doc = "MISC (rw) register accessor: SPI1 misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc`] module"]
230pub type MISC = crate::Reg<misc::MISC_SPEC>;
231#[doc = "SPI1 misc register"]
232pub mod misc;
233#[doc = "TX_CRC (r) register accessor: SPI1 TX CRC data register.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_crc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc`] module"]
234pub type TX_CRC = crate::Reg<tx_crc::TX_CRC_SPEC>;
235#[doc = "SPI1 TX CRC data register."]
236pub mod tx_crc;
237#[doc = "CACHE_FCTRL (rw) register accessor: SPI1 bit mode control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_fctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_fctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_fctrl`] module"]
238pub type CACHE_FCTRL = crate::Reg<cache_fctrl::CACHE_FCTRL_SPEC>;
239#[doc = "SPI1 bit mode control register."]
240pub mod cache_fctrl;
241#[doc = "W (rw) register accessor: SPI1 memory data buffer%s\n\nYou can [`read`](crate::Reg::read) this register and get [`w::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`w::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@w`] module"]
242pub type W = crate::Reg<w::W_SPEC>;
243#[doc = "SPI1 memory data buffer%s"]
244pub mod w;
245#[doc = "FLASH_WAITI_CTRL (rw) register accessor: SPI1 wait idle control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_waiti_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_waiti_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_waiti_ctrl`] module"]
246pub type FLASH_WAITI_CTRL = crate::Reg<flash_waiti_ctrl::FLASH_WAITI_CTRL_SPEC>;
247#[doc = "SPI1 wait idle control register"]
248pub mod flash_waiti_ctrl;
249#[doc = "FLASH_SUS_CTRL (rw) register accessor: SPI1 flash suspend control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sus_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sus_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_sus_ctrl`] module"]
250pub type FLASH_SUS_CTRL = crate::Reg<flash_sus_ctrl::FLASH_SUS_CTRL_SPEC>;
251#[doc = "SPI1 flash suspend control register"]
252pub mod flash_sus_ctrl;
253#[doc = "FLASH_SUS_CMD (rw) register accessor: SPI1 flash suspend command register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sus_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sus_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_sus_cmd`] module"]
254pub type FLASH_SUS_CMD = crate::Reg<flash_sus_cmd::FLASH_SUS_CMD_SPEC>;
255#[doc = "SPI1 flash suspend command register"]
256pub mod flash_sus_cmd;
257#[doc = "SUS_STATUS (rw) register accessor: SPI1 flash suspend status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sus_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sus_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sus_status`] module"]
258pub type SUS_STATUS = crate::Reg<sus_status::SUS_STATUS_SPEC>;
259#[doc = "SPI1 flash suspend status register"]
260pub mod sus_status;
261#[doc = "TIMING_CALI (r) register accessor: SPI1 timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing_cali::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing_cali`] module"]
262pub type TIMING_CALI = crate::Reg<timing_cali::TIMING_CALI_SPEC>;
263#[doc = "SPI1 timing control register"]
264pub mod timing_cali;
265#[doc = "INT_ENA (rw) register accessor: SPI1 interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
266pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
267#[doc = "SPI1 interrupt enable register"]
268pub mod int_ena;
269#[doc = "INT_CLR (w) register accessor: SPI1 interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
270pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
271#[doc = "SPI1 interrupt clear register"]
272pub mod int_clr;
273#[doc = "INT_RAW (rw) register accessor: SPI1 interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
274pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
275#[doc = "SPI1 interrupt raw register"]
276pub mod int_raw;
277#[doc = "INT_ST (r) register accessor: SPI1 interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
278pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
279#[doc = "SPI1 interrupt status register"]
280pub mod int_st;
281#[doc = "CLOCK_GATE (rw) register accessor: SPI1 clk_gate register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
282pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
283#[doc = "SPI1 clk_gate register"]
284pub mod clock_gate;
285#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
286pub type DATE = crate::Reg<date::DATE_SPEC>;
287#[doc = "Version control register"]
288pub mod date;