esp32c2/extmem/
cache_conf_misc.rs

1#[doc = "Register `CACHE_CONF_MISC` reader"]
2pub type R = crate::R<CACHE_CONF_MISC_SPEC>;
3#[doc = "Register `CACHE_CONF_MISC` writer"]
4pub type W = crate::W<CACHE_CONF_MISC_SPEC>;
5#[doc = "Field `CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT` reader - The bit is used to disable checking mmu entry fault by preload operation."]
6pub type CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_R = crate::BitReader;
7#[doc = "Field `CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT` writer - The bit is used to disable checking mmu entry fault by preload operation."]
8pub type CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT` reader - The bit is used to disable checking mmu entry fault by sync operation."]
10pub type CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_R = crate::BitReader;
11#[doc = "Field `CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT` writer - The bit is used to disable checking mmu entry fault by sync operation."]
12pub type CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CACHE_TRACE_ENA` reader - The bit is used to enable cache trace function."]
14pub type CACHE_TRACE_ENA_R = crate::BitReader;
15#[doc = "Field `CACHE_TRACE_ENA` writer - The bit is used to enable cache trace function."]
16pub type CACHE_TRACE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CACHE_MMU_PAGE_SIZE` reader - This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB"]
18pub type CACHE_MMU_PAGE_SIZE_R = crate::FieldReader;
19#[doc = "Field `CACHE_MMU_PAGE_SIZE` writer - This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB"]
20pub type CACHE_MMU_PAGE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21impl R {
22    #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
23    #[inline(always)]
24    pub fn cache_ignore_preload_mmu_entry_fault(&self) -> CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_R {
25        CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - The bit is used to disable checking mmu entry fault by sync operation."]
28    #[inline(always)]
29    pub fn cache_ignore_sync_mmu_entry_fault(&self) -> CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_R {
30        CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - The bit is used to enable cache trace function."]
33    #[inline(always)]
34    pub fn cache_trace_ena(&self) -> CACHE_TRACE_ENA_R {
35        CACHE_TRACE_ENA_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bits 3:4 - This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB"]
38    #[inline(always)]
39    pub fn cache_mmu_page_size(&self) -> CACHE_MMU_PAGE_SIZE_R {
40        CACHE_MMU_PAGE_SIZE_R::new(((self.bits >> 3) & 3) as u8)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CACHE_CONF_MISC")
47            .field(
48                "cache_ignore_preload_mmu_entry_fault",
49                &self.cache_ignore_preload_mmu_entry_fault(),
50            )
51            .field(
52                "cache_ignore_sync_mmu_entry_fault",
53                &self.cache_ignore_sync_mmu_entry_fault(),
54            )
55            .field("cache_trace_ena", &self.cache_trace_ena())
56            .field("cache_mmu_page_size", &self.cache_mmu_page_size())
57            .finish()
58    }
59}
60impl W {
61    #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
62    #[inline(always)]
63    pub fn cache_ignore_preload_mmu_entry_fault(
64        &mut self,
65    ) -> CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
66        CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_W::new(self, 0)
67    }
68    #[doc = "Bit 1 - The bit is used to disable checking mmu entry fault by sync operation."]
69    #[inline(always)]
70    pub fn cache_ignore_sync_mmu_entry_fault(
71        &mut self,
72    ) -> CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W<CACHE_CONF_MISC_SPEC> {
73        CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_W::new(self, 1)
74    }
75    #[doc = "Bit 2 - The bit is used to enable cache trace function."]
76    #[inline(always)]
77    pub fn cache_trace_ena(&mut self) -> CACHE_TRACE_ENA_W<CACHE_CONF_MISC_SPEC> {
78        CACHE_TRACE_ENA_W::new(self, 2)
79    }
80    #[doc = "Bits 3:4 - This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB"]
81    #[inline(always)]
82    pub fn cache_mmu_page_size(&mut self) -> CACHE_MMU_PAGE_SIZE_W<CACHE_CONF_MISC_SPEC> {
83        CACHE_MMU_PAGE_SIZE_W::new(self, 3)
84    }
85}
86#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_conf_misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_conf_misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct CACHE_CONF_MISC_SPEC;
88impl crate::RegisterSpec for CACHE_CONF_MISC_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`cache_conf_misc::R`](R) reader structure"]
92impl crate::Readable for CACHE_CONF_MISC_SPEC {}
93#[doc = "`write(|w| ..)` method takes [`cache_conf_misc::W`](W) writer structure"]
94impl crate::Writable for CACHE_CONF_MISC_SPEC {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets CACHE_CONF_MISC to value 0x07"]
100impl crate::Resettable for CACHE_CONF_MISC_SPEC {
101    const RESET_VALUE: u32 = 0x07;
102}
esp32c2/extmem/cache_conf_misc.rs

esp32c2/extmem/
cache_conf_misc.rs
