Expand description
Masked interrupt status
Structs§
- INT_
ST_ SPEC - Masked interrupt status
Type Aliases§
- DUTY_
CHNG_ END_ CH_ R - Field
DUTY_CHNG_END_CH(0-5)
reader - This is the masked interrupt status bit for the DUTY_CHNG_END_CH%s interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1. - OVF_
CNT_ CH_ R - Field
OVF_CNT_CH(0-5)
reader - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH%s interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1. - R
- Register
INT_ST
reader - TIMER_
OVF_ R - Field
TIMER_OVF(0-3)
reader - This is the masked interrupt status bit for the TIMER%s_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.